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Soft Fault Clustering in Analog Electronic Circuits with the Use of Self Organizing Neural Network

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Języki publikacji
EN
Abstrakty
EN
The paper presents a methodology for parametric fault clustering in analog electronic circuits with the use of a self-organizing artificial neural network. The method proposed here allows fast and efficient circuit diagnosis on the basis of time and/or frequency response which may lead to higher production yield. A self-organizing map (SOM) has been applied in order to cluster all circuit states into possible separate groups. So, it works as a feature selector and classifier. SOM can be fed by raw data (data comes from the time or frequency response) or some pre-processing is done at first. The author proposes conversion of a circuit response with the use of e.g. gradient and differentiation. The main goal of the SOM is to distribute all single faults on a two-dimensional map without state overlapping. The method is aimed for the development stage because the tolerances of elements are not taken into account, however single but parametric faults are considered. Efficiency analyses of fault clustering have been made on several examples e.g. a Sallen-Key BPF and an ECG amplifier. Testing procedure is performed in time and frequency domains for the Sallen-Key BPF with limited number of test points i.e. it is assumed that only input and output pins are available. A similar procedure has been applied to a real ECG amplifier in the frequency domain. Results prove a high efficiency in acceptable time which makes the method very convenient (easy and quick) as a first test in the development stage.
Rocznik
Strony
555--568
Opis fizyczny
Bibliogr. 46 poz., rys., tab., wykr.
Twórcy
autor
  • Faculty of Automatic Control, Electronics and Computer Science, Institute of Electronics, Silesian University of Technology, 16 Akademicka Street, 44-100 Gliwice, Poland, damian.grzechca@polsl.pl
Bibliografia
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  • [7] Golonek, T., Rutkowski, J. (2007). Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection. IEEE Trans. on Cir. and Syst.-II., 54(2), 117-121.
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  • [12] Grzechca, D., Golonek, T., Rutkowski, J. (2007). Simulated Annealing with Fuzzy Fitness Function for Test Frequencies Selection. IEEE Conference on Fuzzy Systems, FUZZ-IEEE, Imperial College London, UK.
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  • [14] Chruszczyk, Ł., Grzechca, D., Rutkowski, J. (September 2007). Finding of optimal excitation signal for testing of analog electronic circuits. Bulletin of the Polish Academy of Science, 55(3), 273-280.
  • [15] Golonek, T., Grzechca, D., Rutkowski, J. (September 14-17, 2008). Optimization of PWL Analog testing Excitation by Means of Genetic Algorithm. Int. Conference on Signals and Electronic Systems, ICSES 2008, 541-548.
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  • [17] Bilski, P., Wojciechowski, M. (2007). Automated Diagnostics of Analog Systems Using Fuzzy Logic Approach. IEEE Trans. on Inst. and Measur., 56(6).
  • [18] Grzechca, D., Golonek, T., Rutkowski, J. (2006). Analog Fault AC Dictionary Creation - The Fuzzy Set Approach. ISCAS 2006, IEEE International Symposium on Circuits and Systems, Kos, Greece, 5744-5747.
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  • [23] Toczek, W. (2004). Analog fault signature based on sigma-delta modulation and oscillation-test methodology. Metrology and Measurement Systems, 11(4), 363-375.
  • [24] Kuczyński, A., Ossowski, M. (2009). Analog circuits diagnosis using discrete wavelet transform of supply current. Metrol. Meas. Syst., 16(1), 77-85.
  • [25] Grzechca, D., Chruszczyk, L. (2007). Wavelet - Neural Network to Analog Paramteric Fault Circuit Location. 13th International Mixed Signals Testing Workshop and 3rd GHz/Gbps Test Workshop, IMSTW&GTW 2007, Povoa de Varzim, Portugal, 2-6.
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  • [27] Jantos, P., Grzechca, D., Rutkowski, J. (2009). Global Parametric Faults identification in analog electronic circuits. Metrol. Meas. Syst., 16(3), 391-402.
  • [28] Czaja, Z., Zielonko, R. (2004). On fault diagnosis of analogue electronic circuits based on transformations in multidimensional spaces. Measurement, 35(3), 293-301.
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  • [32] Toczek, W., Kowalewski, M. (2009). Built-in test scheme for detection, classification and evaluation of nonlinearities. Metrol. Meas. Syst., 16(1), 47-61.
  • [33] Grzechca, D., Rutkowski, J. (2009). Fault Diagnosis in Analog Electronic Circuit - the SVM approach. Metrology and Measurement Systems, 16(4), 583-598.
  • [34] Rutkowski, J. (1994). A two stage neural network DC fault dictionary. Circuits and Systems, 1994. ISCAS ‘94., 1994 IEEE International Symposium on, 6, 299-302.
  • [35] Grzechca, D., Rutkowski, J., Golonek, T. (2010). PCA application to frequency reduction for fault diagnosis in analog and mixed electronic circuit. Proc. of 2010 IEEE Int. Sym. on Circuits and Systems (ISCAS), Paris, France, 1919-1922.
  • [36] Somayajula, S. A. S.; Sanchez-Sinencio, E.; Pineda de Gyvez, J. (1996). Analog fault diagnosis based on ramping power supply current signature clusters. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 43(10), 703-712.
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  • [39] Osowski, S., Siwek, K. (1998). Self-organizing neural network for fault location in electrical circuits. Electronics, Circuits and Systems, 1998 IEEE International Conference on, 2, 265-268.
  • [40] Grzechca, D. (2011). Group of parametric failures in the amplifier with the use of ECG self-organizing neural network. The National Electronics Conference, 896-901. (in Polish)
  • [41] Kohonen, T. (2000). Self Organizing Map. Springer.
  • [42] Kohonen, T. (1988), Self Organization and Associative Memory, Springer Verlag.
  • [43] Mathworks, Self Organizing Map Toolbox.
  • [44] Mehotra, K., Mohan, C. K., Ranka, S. (1997). Elements of Artificial Neural Networks. MIT Press, 187-202.
  • [45] Duch, W., Korbicz, J., Rutkowski, L., Tadeusiewicz, R. (2000). Neural networks, biocybernetics and biomedical engineering. Academic publishing house EXIT. (in Polish)
  • [46] Kugelstadt, T. (2005). Getting the most out of your instrumentation amplifier design. Analog Applications Journal, (4), Analog and Mixed Signal Products, Texas Instruments Incorporated.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW1-0087-0004
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