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Abstrakty
In a parallel time-interleaved data sampling system, timing and amplitude mismatches of this structure degrade the performance of the whole ADC system. In this paper, an adaptive blind synthesis calibration algorithm is proposed, which could estimate the timing, gain and offset errors simultaneously, and calibrate automatically. With no need of an extra calibration signal and redesign, it could efficiently and dynamically track the changes of mismatches due to aging or temperature variation. A fractional delay filter is developed to adjust the timing mismatch, which simplifies the design and decreases the cost. Computer simulations are also included to demonstrate the effectiveness of the proposed method.
Słowa kluczowe
Czasopismo
Rocznik
Tom
Strony
405--414
Opis fizyczny
Bibliogr. 14 poz., rys., wykr.
Twórcy
autor
autor
autor
- University of Electronic Science and Technology of China, College of Automation Engineering, Chengdu, Sichuan, 611731, China, huiqing.pan@gmail.com
Bibliografia
- [1] S.K. Mitra, A. Petraglia: “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer”. IEEE Trans. Instrum. Meas., vol. 40, no. 5, 1991, pp. 831-835.
- [2] C. Vogel, D. Draxelmayr, G. Kubin: “Spectral shaping of timing mismatches in time-interleaved analog-todigital converters”. ISCAS, 2005, pp. 1394-1397.
- [3] C.H. Knapp, G.C. Carter: “The generalized correlation method for estimation of time delay”. IEEE Trans Acoust Speech Signal Proces., vol. ASSP-24, 1976, pp. 320-327.
- [4] Y.C. Jenq: “Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving”. IEEE Trans. Instrum. Meas., vol. 39, no. 1, 1990, pp. 71-75.
- [5] J.E. Eklund, F. Gustafsson: “Digital offset compensation of time-interleaved ADC using random chopper sampling”. ISCAS, vol. 3, 2000, pp. 447-450.
- [6] S. Jamal, F. Daihong, N. Chang, P. Hurst, S. Lewis: “A 10-b 120-Msample/s time-interleaved analog-todigital converter with digital background calibration”. IEEE J. Solid-State Circ., vol. 37, 2002, pp. 1618-1627.
- [7] H.C. So, P.C. Ching, Y.T. Chan: “A new algorithm for explicit adaptation of time delay”. IEEE Trans. Signal Proces., vol. 42, no. 7, 1994, pp. 1816-1820.
- [8] D. Fu, K.C. Dyer, S.H. Lewis, P.J. Hurst: “A digital background calibration technique for time-interleaved analog-to-digital converters”. IEEE J. Solid-State Circ., vol. 33, 1998, pp. 1904-1911.
- [9] T. Ndjountche, R. Unbehauen: “Adaptive calibration techniques for time-interleaved ADCs”. Electronic Letter, vol. 37, 2001, pp. 412-414.
- [10]L. Jian, W.R. Biao: “An efficient algorithm for time delay estimation”. IEEE Trans. Signal Proces., vol. 46, no. 8, 1998, pp. 2231-2235.
- [11]Y.K. Juha, S. Tapio: “Multiplier-free polynomial-based FIR filters with an adjustable fractional delay”. IEEE Trans. Circ., Syst., Signal Proces., vol. 25, no. 2, 2006, pp. 265-294.
- [12]T. Coleman, M.A. Branch, A. Grace: Optimization Toolbox User’s Guide Version 2, The MathWorks Inc., 1999, pp. 282-298.
- [13] http://www.analog.com/en/analog-to-digital-converters/ad-converter/products/evaluationboardstools/CU_A DIsimADC_evaluation_tools/resources/fca.html.
- [14]F.C. Alegria: “Study of the Random Noise Test of Analog-to-Digital Converters”. Metrol. Meas. Syst., vol. XVI, no. 4, 2009, pp. 545-556.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW1-0069-0008