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Global parametric fault identification in analog electronic circuits

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
A method of global parametric fault diagnosis in analog integrated circuits is presented in this paper. The method is based on basic features calculated from a circuit under the test's time domain response to a voltage step, i.e. locations of maxima and minima of the circuit-under-test response and its first order derivative. The testing and diagnosis process is executed with the use of an artificial neural network. The neural network is supplied with extracted basic features. After evaluation and discrimination, the output indicates the circuit state. The proposed diagnosis method has been verified with the use of exemplary integrated circuits - an operational amplifier μA741, a sinewave oscillator and an integrated band-pass filter.
Rocznik
Strony
391--402
Opis fizyczny
Bibliogr. 23 poz., rys., tab., wzory
Twórcy
autor
autor
autor
  • Silesian University of Technology, Institute of Electronics, Faculty of Automatic Control, Electronics and Computer Science, Akademicka 16, 44-100 Gliwice, Poland, pjantos@polsl.pl
Bibliografia
  • [1] P. Kabisatpathy, A. Barula, S. Sinha: Fault Diagnosis in Analogue Integrated Circuits. Springer, 2005.
  • [2] K.R. Laker, W.M.C. Sansen: Design of Analgo Integrated Circuits and Systems. MacGraw-Hill, 1994.
  • [3] S. Chakrabarti, S. Cherubal, A. Chatterjee: “Fault diagnosis for mixed-signal electronic systems, Aerospace Conference 1999”. Proceedings 1999 IEEE, vol. 3, 1999, pp. 169-179.
  • [4] S. Cherubal, A. Chatterjee: “Test generation based diagnosis of device parameters for analog circuits”. DATE ‘01: Proceedings of the conference on Design, automation and test in Europe, Munich, Germany, 2001, pp. 596-602.
  • [5] S. Chakrabarti, A. Chatterjee: “Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits”. Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI (ARVLSI ‘99), Atlanta, USA, 1999, pp. 327-341.
  • [6] T. Ytterdal, Y. Cheng, T. Fjeldly: Device Modeling for Analog and RF CMOS Circuit Design. Wiley, 2003.
  • [7] P. van Zant: Microchip Fabrication: A Practical Guide to Semiconductor Processing. McGraw-Hill, 2004.
  • [8] Q. Ming, M.A. Styblinski: “An efficient approach to device parameter extraction for statistical IC modelling”, Custom Integrated Circuits Conference. Proceedings of the IEEE, San Diego, USA, 1996, pp. 329-332.
  • [9] Q. Ming, M.A. Styblinski: “Parameter Extraction for Statistical IC Modelling Based on Recursive Inverse Approximation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 11, 1997, pp.1250-1259.
  • [10]C.J.B. Spanos, S.W. Director: “Parameter Extraction for Statistical IC Process Characterization.” IEEE Transactions on Computer-Aided Design, vol. CAD-5, no. 1, 1986, pp. 66-78.
  • [11]L. Zhou, Y. Shi, J. Tang, Y. Li: “Soft Fault Diagnosis in Analog Circuit Based on Fuzzy and Direction Vector”. Metrol Meas Syst, vol. XVI, no. 1, 2009, pp. 61-76.
  • [12]A. Kuczyński, M. Ossowski: “Analog circuit diagnosis using discrete wavelet transform of supply current”. Metrol Meas Syst, vol. XVI, no. 1, 2009, pp. 77-84.
  • [13]Z. Czaja, R. Zielonko: “On fault diagnosis of analog electronic circuits based on transformations in multidimensional spaces”. Measurement, no. 35, 2004, pp. 293-301.
  • [14]V. Litovski, M. Andrejevic, M. Zwolinski: “Analog electronic circuit diagnosis based on ANNs. Active and Passive Electronic Components”. Microelectronics and reliability, vol. 46, 2006, pp. 1382-1391.
  • [15]P. Jantos, D. Grzechca, T. Golonek, J. Rutkowski: “The Influence of Global Parametric Faults on Analog Electronic Circuits Time Domain Response Features”. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, Ostrava, Czech Republic, pp. 299-303.
  • [16]P. Jantos, D. Grzechca, T. Golonek, J. Rutkowski: “Global Parametric Faults in Analog Electronic Integrated Circuits: Two Approaches to Classification with the Use of Differential Evolution”. The 2nd European Computing Conference, ECC’08, sponsored by WSEAS, New Aspects on Computing Research, WSEAS Press, Malta, vol. 1, 2008, pp. 281-286.
  • [17]P. Jantos, D. Grzechca, J. Rutkowski: “Identyfikacja globalnych uszkodzeń parametrycznych w analogowych układach scalonych”. Krajowa Konferencja Elektroniki, 2009, Darłówko Wschodnie, pp. 57. (in Polish)
  • [18]P. Jantos, D. Grzechca, J. Rutkowski: “Global Parametric Faults Identification with the Use of Differential Evolution”. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Liberec, Czech Republic, 2009, pp. 222-225.
  • [19]J. Savir, Z. Guo: “The Limitations of Parametric Faults in Analog Circuits”. IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 5, 2003.
  • [20]M.A. Arbib: The Handbook of Brain Theory and Neural Networks. The MIT Press, 2003.
  • [21]J.A. Freeman, D.M. Skapura: Neural Networks: Algorithms, Applications and Programming Techniques. Addison-Wesley Publishing Company, 1991.
  • [22]S. Haykin: Neural Networks: A comprehensive foundation. Pearson Education, USA, 1999.
  • [23]N.K. Kasabov: Foundation of Neural Networks, Fuzzy Systems and Knowledge Engineering. The MIT Press, 1998.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW1-0059-0005
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