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Digital-to-analog conversion using delta-sigma modulators implemented in Virtex-4 FPGA devices

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This paper presents some selected architectures of delta-sigma modulators which are suitable for implementation of digital-to-analog converters (DACs) in modern FPGA devices. Simulation and implementation of simple architectures of first and second order of digital-to-analog converters in FPGA chip is described. Experimental tests have been performed using the evaluation board ML401 from Xilinx, based on the XC4VLX25 Virtex-4 chip. The quality of DACs has been measured and described by relevant power spectrum diagrams and differential linearity functions. Detailed comparison of DAC architectures is also given in terms of used resources and maximum operating frequency. It has been shown that carefully designed delta-sigma modulators implemented using modern FPGA technology are competitive to conventional integrated DACs. Consequently, multichannel DACs and ADCs of good quality can be designed within the FPGA chip. In this way, the idea of single-chip measurement system containing all essential parts as DACs, ADCs, CPU and digital I/O becomes an interesting alternative to the classical approach based on the multi-chip and/or ASIC technology.
Rocznik
Strony
409--427
Opis fizyczny
Bibliogr. 21 poz., rys., wykr.
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autor
autor
Bibliografia
  • 1. Ludewig R., et. al: IP Generation for an FPGA-based Audio DAC Delta-sigma Converter, In Proc. of the International Conference on Field Programmable Logic and Applications, 2004.
  • 2. Norsworthy S. R., Schreier R., Temes G. C.: Delta-Sigma Data Converters, New York, IEEE Press, 1997.
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  • 4. Melgarejo M. A.: Minimum area FPGA implementation of a first order sigma delta modulator, GSPx Conference Paper, 2003.
  • 5. Logue J.: Virtex Synthesizable Delta-Sigma DAC, XAPP 154, Xilinx, 1999.
  • 6. Logue J.: Virtex Analog to Digital Converter, XAPP 155, Xilinx, 1999.
  • 7. Park S.: Principles of Delta-sigma Modulation for Analog-to-Digital Conversion, APR8/D Rev. 1, Motorola.
  • 8. Candy J. C., Temes G. C.: Oversampling delta-sigma data converters, Theory, design, and simulation, IEEE-Wiley Interscience, 1992.
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  • 10. Friedman V.: The structure of the limit cycles in sigma delta modulation, IEEE Trans. COM, vol. 36, no. 8, pp. 972-979, 1988.
  • 11. Feely O., Chua L. O.: The effect of integrator leak in delta-sigma modulation, IEEE Trans. CAS, vol. 38, no. 11, pp. 1293-1305, 1991.
  • 12. Reiss J. D., Sandler M. B.: They exist: Limit cycles in high order sigma delta modulators, In Proc. 114th Convention of the Audio Engineering Society, 2003.
  • 13. Matsuya Y., Uchimura K., Iwata A.: A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping, IEEE J. Solid-State Circuits, SSC-22, pp. 921-929, 1987.
  • 14. Virtex-4 Handbook, Xilinx, 2004.
  • 15. Knapp S. K.: Using Programmable Logic to Accelerate DSP Functions, Xilinx, 1995.
  • 16. Harris F., Dick C.: FPGA signal processing using delta-sigma modulation, Xilinx, 1999.
  • 17. Harris F., Dick C.: High performance filters using delta-sigma modulation encoding, Xilinx, 1999.
  • 18. Gray R.: Oversampled sigma-delta modulation, IEEE Trans. on communications, vol. COM-35, pp. 481-488, 1987.
  • 19. Alfke P.: Efficient shift registers, LFSR counters, and long pseudo-random sequence generators, XAPP 052, 1996.
  • 20. Agilent mulitimeter 34401A, http://www.home.agilent.com/USeng/nav/-536902435.536880933/pd.html.
  • 21. Delta-sigma DAC’s projects, http://ztc.wel.wat.edu.pl/ztc.htm.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW1-0038-0006
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