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### Synteza logiczna przeznaczona dla matrycowych struktur programowalnych typu PAL

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The logic synthesis for the PAL-based complex programmable logic devices
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PL
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PL
EN
The logic presents the synthesis for CPLDs. The core of CPLDs is a PAL-based structure which consists of the programmable AND matrix and fixed connections within the OR matrix. These matrixes form the PAL-based logic blocks. The aim of the work is to present the synthesis method of which enables implementation of a Boolean function by the means of the PAL-based logic blocks containing a definite number of terms. The first method is based on a unique of the multi-output Boolean function. The essence of the method concentrates on the process of searching for the common multi-output implicants based on the analysis of graph's nodes representing the output vectors. The suggested algorithms of synthesis have their foundation in the theorem on choosing a node of the graph outpust. That theorem serves as a theoretical background for the selection of those implicants' groups that are realized by the means of the shared PAL-based logic blocks. In a case of not meeting the conditions of the theorem by the nodes of the graph outpust to choose the specific node, a selection of the implicants' group is carried out according to the heurestic rules. Moreover, in this part of work, a new method for the description of feedback can be found, which leads to the appropriate modification of those nodes constituting the graph of outpust. The logic blocks that occur within the CPLD structures include frequently the additional logic resources. There are, among other things, such resources as the three-state output buffers, which can be taken into account in the process of logic synthesis. First, the process of synthesis starts with the two-level splitting minimization procedure. Then, a partition of the individual implicants' groups takes place. As a result of the two procedures mentioned above, the initial set of the Boolean function's implicants is divided into subsets with the higher or equal cardinality to the number of terms within the certain PAL-based logic blocks. Decomposition is an extremely valuable component of synthesis. First of all, it influences directly the number of logical blocks. The unusal application of the classical theory on the decomposition is discussed in the second part of this work. The algorithms developed are derived from the classical model of the functional decomposition that was introduced by Curtis. The individual phases of the decomposition are prepared for the PAL-based CPLD structures. The designed method for the row decomposition of the single-output Boolean function enables the adjustment of the obtained sub-circuits with the certain structure of the PAL-based logic block. The theoretical considerations serve as a base for the synthesis of algorithms included in this work. The final part of the work presents the complex strategies of synthesis, aimed at the various CPLD circuits (with/without the three-state output buffers). The strategies of synthesis are designed for the optimization following either the number of logical blocks or the number of levels. The individual synthesis methods, presented in the previous chapters, serve as the components of those strategies. The work presents also a number of results obtained from experiments. The experiments were carried out for the commonly used benchmarks, applying various families of programmable devices. The designed strategies were compared with the university-developed and the commercially available tools of the synthesis.
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PL
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5--212
Opis fizyczny
bibliogr. 223
Twórcy
autor
• Instytut Elektroniki Politechnika Śląska, 44-100 Gliwice, ul. Akademicka 16 tel. (032) 237-26-14, dariusz.kania@polsl.pl
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