Synthesis of finite state machines for CPLDs

• Autorzy: Czerwiński R. , Kania D.
• Języki publikacji: EN

Abstrakty

EN

The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

Słowa kluczowe

EN

logic synthesis; FSM; state assignment; logic optimization; CPLD

PL

synteza logiczna; FSM; kodowanie stanów; optymalizacja logiczna; CPLD

• Wydawca: Oficyna Wydawnicza Uniwersytetu Zielonogórskiego
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2009
• Tom: Vol. 19, no 4
• Strony: 647--659
• Opis fizyczny: Bibliogr. 22 poz., rys., tab., wykr.

Twórcy

autor

Czerwiński R.

• Institute of Electronics Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland

autor

Kania D.

• Institute of Electronics Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland

Bibliografia

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