Reduction in the number of PAL macrocells in the ciruit of a Moore FSM

• Autorzy: Barkalov A. A. , Titarenko L. , Chmielewski S.
• Języki publikacji: EN

Abstrakty

EN

Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

Słowa kluczowe

EN

Moore finite-state machine; complex programmable logic devices; design; logic circuit; pseudoequivalent states

PL

automat Moore'a; złożone programowalne układy logiczne; układ logiczny; stan pseudorównoważny

• Wydawca: Oficyna Wydawnicza Uniwersytetu Zielonogórskiego
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2007
• Tom: Vol. 17, no 4
• Strony: 565--575
• Opis fizyczny: Bibliogr. 20 poz., rys., wykr., tab.

Twórcy

autor

Barkalov A. A.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

autor

Titarenko L.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

autor

Chmielewski S.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

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