FSM encoding for BDD representations

• Autorzy: Gosti W. , Villa T. , Saldanha A. , Sangiovanni-Vincentelli A. L.
• Języki publikacji: EN

Abstrakty

EN

We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function has the minimum number of nodes. We present an exact algorithm to solve this problem when only the present state variables are encoded. We provide results on MCNC benchmark circuits.

Słowa kluczowe

EN

binary decision diagram; encoding; finite state machine; logic synthesis; formal verification; logic representation

PL

binarny diagram decyzyjny; kodowanie; automat skończony; synteza logiczna; weryfikacja formalna

• Wydawca: Oficyna Wydawnicza Uniwersytetu Zielonogórskiego
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2007
• Tom: Vol. 17, no 1
• Strony: 113--128
• Opis fizyczny: Bibliogr. 25 poz., rys., tab.

Twórcy

autor

Gosti W.

• Cadence Design Systems, 2655 Seely Avenue, San Jose, CA 95134

autor

Villa T.

• DI, Universita’ di Verona, Ca’ Vignal 2, Strada Le Grazie 15, 37134 Verona, Italy; PARADES, Via S.Pantaleo,66 , 00186 Roma, Italy

autor

Saldanha A.

• Exponential Interactive, Inc., Emeryville, CA 94608, USA

autor

Sangiovanni-Vincentelli A. L.

• PARADES, Via S.Pantaleo,66 , 00186 Roma, Italy; Department of Electrical Engineering and Computer Sience, University of California, Berkeley, CA 94720, USA

Bibliografia

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