Scaling of nonvolatile memories to nanoscale feature sizes

• Autorzy: Mikolajick T. , Nagel N. , Riedel S. , Mueller T. , Kusters K. H.
• Języki publikacji: EN

Abstrakty

EN

he market for nonvolatile memory devices is growing rapidly. Today, the vast majority of nonvolatile memory devices are based on the floating gate device which is facing serious scaling limitations. Material innovations currently under investigation to extend the scalability of floating gate devices are discussed. An alternative path is to replace the floating gate by a charge trapping material. The combination of charge trapping and localized channel hot electron injection allows storing two physically separated bits in one memory cell. The current status and prospects of charge trapping devices are reviewed, demonstrating their superior scalability. Floating gate as well as charge trapping memory cells suffer from severe performance limitations with respect to write and erase speed and endurance driving system overhead. A memory that works like random access memory and is nonvolatile would simplify system design. This, however, calls for new switching effects that are based on integrating new materials into the memory cell. An outlook to memory concepts that use ferroelectric switching, magnetic switching, phase change, or other resistive switching effects is given, illustrating how the integration of new materials may solve the limitations of today's semiconductor memory concepts.

Słowa kluczowe

EN

nonvolatile memories; flash memories; NAND; organic memories; molecular memories

PL

pamięci nieulotne; pamięć błyskowa; pamięci magnetyczne; pamięć molekularna

• Wydawca: De Gruyter
• Czasopismo: Materials Science Poland
• Rocznik: 2007
• Tom: Vol. 25, No. 1
• Strony: 33--43
• Opis fizyczny: Bibliogr. 36 poz.

Twórcy

autor

Mikolajick T.

autor

Nagel N.

autor

Riedel S.

autor

Mueller T.

autor

Kusters K. H.

• Qimonda Dresden GmbH & Co. OHG, Technology Center flash QD TC FL, Dresden, Germany,

Bibliografia

• [1] NIEBEL A., Proc. of the 20th Nonvolatile Semiconductor Memory Workshop, Monterey, California (2004), p. 14.
• [2] BYEON D.-S., LEE S.-S., LIM Y.-H., PARK, J.-S., HAN W.-K., KWAK P.-S., KIM D.-H., CHAE D.-H., MOON S.-H., LEE S.-J., CHO H.-C., LEE J.-W., KIM M.-S., YANG J.-S., PARK Y.-W., BAE D.-W., CHOI J.-D., HUR S.-H., SUH K.-D., Proc. Int. Solid State Circuits Conference, IEEE, San Francisco (2005), p. 46.
• [3] PAVAN P., BEZ R., OLIVO P., ZANONI E., Proc. IEEE, 85 (1997), 1248.
• [4] LAI S., Proc. Seventh Biennial International Nonvolatile Memory Technology Conference, IEEE, Albuquerque (1998), p. 6.
• [5] LIKHAREV K., Appl. Phys. Lett., 73 (1998), 2137.
• [6] CASPERSON J., J. Appl. Phys., 92 (2002), 261.
• [7] LEE W.-H., CLEMENS J.T., KELLER R.C., MANCHANDA L., VLSI Technology Digest of Technical Papers (1997), p. 117.
• [8] LEE J.-D., SUNG-HOI H., CHOI J.-D., IEEE Electr. Device Lett., 23 (2002), 264.
• [9] CHOI S., CHO M., HWANG H., KIM J.W., J. Appl. Phys., 94 (2003), 5408.
• [10] BACHHOFER H., REISINGER H., BERTAGNOLLI E., VON PHILIPSBORN H., J. Appl. Phys., 89 (2001), 2791.
• [11] LEE C.-H., PARK K.-C., KIM K., Appl. Phys. Lett., 86 (2005), 73510.
• [12] SHIN Y., CHOI J., KANG C., LEE C., PARK K.-T., LEE J.-S., SEL J., KIM V., CHOI B., SIM J., KIM D., CHO H.-J., KIM K., IEDM Digest Techn. Papers, IEEE (2005), p. 327.
• [13] ISHIMARU T., MATSUZAKI N., OKUYAMA Y., MINE T., WATANABE K., YUGAMI J., KUME H., ITO F., KAWASHIMA Y., SAKAI T., KANAMARU Y, ISHII Y., MIZUNO M., ISHII Y., MIZUNO M., KAMOHARA S., HASHIMOTO T., OKUYAMA K., KURODA K., KUBOTA K., IEDM Digest Techn. Papers. IEEE (2004), p. 885
• [14] TAN Y.-N., CHIM W.-K., BYUN J.C., WEE-KIONG C., IEEE Trans. Electr. Devices 51 (2004), 1143.
• [15] CHAN T.Y., IEEE Electr. Device Lett., 8 (1987), 93.
• [16] EITAN B., PAVAN P., BLOOM I., ALONI E., FROMMER A., FINZ D., IEEE Electr. Device Lett., 21 (2000), 543.
• [17] NAGEL N., OLLIGS, D., POLEI, V., PARASCANDOLA S., BOUBEKEUR H., BACH L., MULLER T., STRASSBURG M., RIEDEL S., KRATZERT P., CASPARY D., DEPPE J., WILIER J., SCHULZE J., SCHULZE N., MIKOLAJICK T., KUSTERS K.-H., SHAPPIR A., REDMARD E., BLOOM I., EITAN B., VLSI Techn. Digest Techn. Papers, Kyoto (2005), p. 120.
• [18] STEIN V., KAMIENSKI E.G., ISLER M., MIKOLAJICK T., LUDWIG C., SCHULZE N., NAGEL N., RIEDEL S., WILLER J., KÜSTERS K.-H., Proc. Non-Volatile Memory Technology Symposium, Dallas, 2005, p. 5.
• [19] WILLER J., LUDWIG C., DEPPE J., KLEINT C., LAU F., PALM H., EITAN B., BLOOM I., Proc. 19th Nonvolatile Semiconductor Memory Workshop, Monterey, California (2003), p. 42.
• [20] SUGIZAKI T., KOBAYASHI M., ISHIDAO M., MINAKATA H., YAMAGUCHI M., TAMURA Y., SUGIYAMA Y., NAKANISHI T., TANAKA H., VLSI Techn. Digest Techn. Papers, Kyoto (2003), p. 27.
• [21] PINNOW C.-U., MIKOLAJICK T., J. Electrochem. Soc., 151 (2004), K1.
• [22] Materials for Information Technology, E. Zschech, C. Whelan, T. Mikolajick (Eds.), Springer, London, 2005, p. 112.
• [23] MIKOLAJICK T., DEHM C., HARTNER W., KASKO I., KASTNER M.J., NAGEL N., MOERT M., MAZURE C., Microelectronics Reliability, 41 (2001), 947.
• [24] LEE S.Y., Extended Abstracts of the International Conference on Solid State Devices and Materials, Kobe, Japan (2005), p. 1026.
• [25] KOO JU.M., SEO B.-S., KIM S., SHIN S., LEE J.-H., BAIK H., LEE.J.-H., LEE J.H., BAE B.-J., LIM. J.-E., YOO D.-C., PARK S.-O., KIM H.-S., HAN H., BAIK S., CHOI J.-Y., PARK Y.J., PARK Y., IEDM Digest Tech. Papers, IEEE (2005), p. 4.
• [26] GALAGHER W.J., IEEE VLSI-TSA Int. Symp. VLSI Technology, Kyoto, Japan (2005), p. 72.
• [27] HOSOMI M., YAMAGISHI H., YAMAMOTO T., BESSHO K., HIGO Y., YAMANE K., YAMADA H., SHOJI M., HACHINO H., FUKUMOTO C., NAGAO H., KANO H., IEDM Digest Techn. Papers, IEEE (2005), p. 459.
• [28] HUDGENS S., JOHNSON B., MRS Bull. November (2004), p. 829.
• [29] OH H.-R., IEEE J. Solid State Circuits, 41 (2006), 122.
• [30] SECZI R., WALTER A., ENGL R., MALTENBERGER A., SCHUMANN J., KUND M., DEHM C., IEDM Digest Techn. Papers IEEE (2003), 10.2.1.
• [31] YANG Y., Organic Nonvolatile Memories, in [22], p. 197.
• [32] KRIEGER J.H., SPITZER S.M., Proc. Non-Volatile Memory Technology Symposium, Orlando-Florida (2004), p. 121.
• [33] LUO Y., COLLIER C.P., JEPPESEN, J.O., NIELSEN K.A., DEIONNO E., HO G., PERKINS J., TSENG H.-R., YAMAMOTO T., FRASER STODDART J., HEATH, J. R., ChemPhysChem, 3 (2002), 519.
• [34] ROTH K.M., DONTHA N., DABKE R.B., GRYKO D.T., CLAUSEN C., LINDSEY J.S., BOCIAN D.F., KUHR W.G., J. Vac. Sci. Technol., B 18, (2000), 2359.
• [35] REED M. A., CHEN J., RAWLETT A.M., PRICE D.W., TOUR J.M., Appl. Phys. Lett., 78 (2001), 3735.
• [36] RUECKES T., KIM K., JOSELEVICH E., TSENG G.Y., CHEUNG C.-L., LIEBER C.M., Science, 289 (2000), 94.