Multiple tasks in FPGA-based programmable controller

• Autorzy: Hajduk Z. , Sadolewski J.
• Języki publikacji: EN

Abstrakty

EN

An FPGA-based execution platform for PLC controllers with capability to run multiple control tasks is presented. The platform, called multi-CPCore, uses hardware virtual machines to execute control tasks defined in CPDev engineering environment. The tasks consist of one or more programs written in IEC 61131-3 languages, such as ST, IL or FBD. They may run with different cycles and communicate via global variables. Parallel programming mechanisms like process image and semaphores are provided to handle potential conflicts when accessing shared resources.

Słowa kluczowe

EN

FPGA; parallel programming; based execution platform

• Wydawca: Oficyna Wydawnicza Politechniki Wrocławskiej
• Czasopismo: e-Informatica Software Engineering Journal
• Rocznik: 2011
• Tom: Vol. 5, nr 1
• Strony: 77--85
• Opis fizyczny: Bibliogr. 9 poz.

Twórcy

autor

Hajduk Z.

autor

Sadolewski J.

• Faculty of Electrical and Computer Engineering, Department of Computer and Control Engineering, Rzeszow University of Technology,

Bibliografia

• [1] Z. Hajduk, B. Trybus, and J. Sadolewski, “Hardware implementation of virtual machine for programmable controllers,” in Metody wytwarzania i zastosowania systemów czasu rzeczywistego, L. Trybus and S. Samolej, Eds. Warszawa: Wydawnictwa Komunikacji i Łacznosci, 2010, ch. Chapter 5, pp. 333–342, (in Polish).
• [2] IEC 61131-3 standard: Programmable Controllers – Part 3. Programming Languages, IEC Std., 2003.
• [3] D. Rzonca, J. Sadolewski, A. Stec, Z. Swider,B. Trybus, and L. Trybus, “Open environment for programming small controllers according to IEC 61131-3 standard,” Scalable Computing: Practice and Experience, vol. Volume 10, no. 3, pp. 325–336, 2009.
• [4] D. Gawali and V. Sharma, “FPGA Based Micro-PLC Design Approach,” Advances in Computing, Control, and Telecommunication Technologies, International Conference on, vol. 0, pp. 660–663, 2009.
• [5] M. Adamski and J. L. Monteiro, “From interpreted Petri net specification to reprogrammable logic controller design,” in Proc. IEEE Int. Symp. Industrial Electronics (ISIE 2000), vol. 1, 2000, pp. 13–19.
• [6] P. Huerta, J. Castillo, C. Pedraza, J. Cano, and J. I. Martinez, “Symmetric multiprocessor systems on FPGA,” in IEEE Int. Conf. on Reconfigurable Computing and FPGAs. ReConFig ’09,2009, pp. 279–283.
• [7] Z. Hajduk, “Floating-point arithmetic unit for a hardware virtual machine,” Pomiary Automatyka Kontrola, vol. 57, no. 1, pp. 82–85, 2011, (in Polish).
• [8] “Communication module for a hardware implemented virtual machine,” Elektronika – konstrukcje, technologie, zastosowania, no. 5, 2011,(in Polish).
• [9] “PLC controller prototype with a hardware virtual machine,” Elektronika – konstrukcje, technologie, zastosowania, no. 4, pp. 114–118, 2011, (in Polish).