PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Tytuł artykułu

CMOS evolution. Development limits

Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Evolution of complementary metal oxide semiconductor (CMOS) technology is presented from the very first MOS transistors to state-of-the-art structures. Difficulties of scaling are discussed together with ways to overcome them. New options for silicon microelectronics (SOI technology and strain engineering) are described. Finally, fundamental limitations to progress in semiconductor devices are considered.
Wydawca
Rocznik
Strony
5--20
Opis fizyczny
Bibliogr. 34 poz.
Twórcy
autor
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland
Bibliografia
  • [1] MOORE G.E., Progress in digital integrated electronics, IEEE Int. Dev. Meeting, Dig., 1975, p. 103
  • [2] KURZWEIL R., The Singularity Is Near, Penguin Books, 2005.
  • [3] DENNARD R.H., GAENSSLEN F.H., YU H.-N., RIDEOUT V.L., BASOUS E., LEBLANC A.R., IEEE J. Solid-State Circuits, 9 (1974), 256.
  • [4] SAH C.-T., Proc. IEEE, 76 (1988), 1280.
  • [5] LILIENFELD J.E., Device for controlling electric current, U.S. Patent 1 900 018. Application filed Mar. 28, 1928, granted Mar. 7, 1933.
  • [6] ATALLA M.M., TANENBAUM M., SHEIBNER E.J., Bell Syst. Tech. J., 38 (1959), 123.
  • [7] KAHNG D., ATALLA M.M., Silicon–silicon dioxide field induced surface devices, Proc. IRE-AIEE Solid-State Device Research Conference, Carnegie Institute of Technology, Pittsburgh, U.S.A., 1960.
  • [8] WANLASS F.M., SAH C.T., Nanowatt logic using field-effect metal-oxide semiconductor triodes, [in:] Technical Digest of the IEEE, Int. Solid-State Circuit Conf., 20.02.1963, pp. 32–33.
  • [9] KERWIN R.E., KLEIN D.L., SARACE J.C., Method for making MIS structures, U.S. Patent 3 475 234, filed Mar. 27, 1967, issued Oct. 28, 1969.
  • [10] YAU L.D., Solid State Electron., 17 (1974), 1059.
  • [11] TROUTMAN R.R., IEEE Trans. Electron. Dev., 26 (1979), 461.
  • [12] BREWS J.R., FICHTNER W., NICOLLIAN E.H., SZE S.N., IEEE Electron Dev. Lett., 1 (1980), 2.
  • [13] HUNTER W.R., HOLLOWAY T.C., CHATTERJEE P.K., TASCH A.F., IEDM Tech. Dig. (1980), 764.
  • [14] WONG S.S., BRADBURY D.R., CHEN D.C., CHIU K.Y., IEDM Tech. Dig. (1984), 634.
  • [15] MOCHIZUKI T., WISE K.D., IEEE Electron Dev. Lett., 5 (1984), 108.
  • [16] GHANI T., MISTRY K., PACKAN P., THOMPSON S., STETTLER M., TYAGI S., BOHR M., Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors, Symp. VLSI Technology Dig. Tech. Papers, 2000, pp. 174–175.
  • [17] OGURA S., CODELLA C.F., ROVEDO N., SHEPARD J.F., RISEMAN J., IEDM Tech. Dig. (1982), 718.
  • [18] TIAN H., HULFACHOR R.B., ELLIS-MONAGHAN J.J., KIM K.W., LITTLEJOHN M.A., HAUSER J.R., MASNARI N.A., , IEEE Trans. Electron Dev., 41 (1994), 1880.
  • [19] CROWDER B.L., ZIRINSKI S., IEEE Trans. Electron Dev., 26 (1979), 369.
  • [20] MOHIZUKI T., SHIBATA K., INOUE T., OBUCHI K., KASHIWOGI M., ECS Extended Abstracts, 72-2 (1977), 331.
  • [21] SARASWAT K.C., MOHAMMEDI F., MEINDL J.D., IEDM Tech. Dig. (1979), 462.
  • [22] TING C.Y., IYER S.S., OSBURN C.M., HU G.IJ., SCHWEIGHART A.M., The use of TiSi2 in a self-aligned silicide technology, ECS Extended Abstracts, 82-2 (1982), 254.
  • [23] CHUANG C.-T., BERNSTEIN K., JOSHI R.V., PURI R., KIM K., NOWAK E.J., LUDWIG T., ALLER I., IEEE Circuits Dev. Mag., Jan./Feb. 2004, 6.
  • [24] ZEITZOFF P.M., CHUNG J.E., IEEE Circuits Dev. Mag., Jan/Feb 2005, 4.
  • [25] LUNDSTROM M., GUO J., Nanoscale Transistors – Device Physics, Modeling and Simulation, Springer, New York, 2005.
  • [26] WONG H.-S.P., Solid State Electron., 49 (2005), 755.
  • [27] COLLINGE J.-P., Silicon-on-Insulator Technology: Materials to VLSI, Kluwer, Boston, 2004.
  • [28] SKOTNICKI T., HUTCHBY J.A., KING T.-J., WONG H.-S.P., BOEUF F., IEEE Circuits Dev. Mag., Jan./Feb. 2005, p. 16.
  • [29] NOWAK E.J., ALLER I., LUDWIG T., KIM K., JOSHI R.V., CHUANG C.-T., BERNSTEIN K., PURI R., Turning silicon on its edge, IEEE Circuits Dev. Mag., Jan/Feb 2004, p. 20.
  • [30] COLINGE J.-P., Solid State Electron., 48 (2004), 897.
  • [31] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2006.
  • [32] MOHTA N., THOMPSON S.E., Mobility enhancement, IEEE Circuits Dev. Mag., Sept/Oct, 2005, p. 18.
  • [33] LLOYD S., Nature, 406 (2000), 1047.
  • [34] ZHIRNOV V.V., CAVIN R.K., HUTCHBY J.A., BOURIANOFF G.I., Proc. IEEE, 91 (2003), 1934.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPW7-0007-0161
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.