Tytuł artykułu
Autorzy
Identyfikatory
Warianty tytułu
Konferencja
19th IMEKO TC-10 International Conference on Technical Diagnostics. Integration in Technical Diagnostics (22-24.09.1999 ; Wrocław)
Języki publikacji
Abstrakty
The paper deals with fault location of the PWL type analog circuits based on verification approach and hybrid equations. In the first part of the paper the diagnostic equation, fault models and algorithm of the method are described. For verification of fault hypothesis the residual square sum criterion is applied. Theoretical considerations have been illustrated by example of single fault diagnosis of the three-stage transistor amplifier. The method could be used also to diagnosis of circuits with multiple faults.
Rocznik
Tom
Strony
218--223
Opis fizyczny
Bibliogr. 6 poz, rys. 6
Twórcy
autor
autor
- Technical University of Gdańsk, Chair of Electronic Measurement, Narutowicza 11/12 Street, 80-952 Gdańsk, Poland
Bibliografia
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPW2-0003-0088