Gaps in design and tests of dependable embedded systems

• Autorzy: Grobelna I. , Grobelny M.

Warianty tytułu

PL

Luki w zakresie projektowania i testów niezawodnych systemów wbudowanych

• Języki publikacji: EN

Abstrakty

EN

The paper focuses on gaps in design and test technology for dependable embedded systems. Possible gaps in design may influence system behavior and as the result final product may not fulfill all requirements or some of desired properties. Test phase is also important as it may indicate even subtle errors which occurred in previous phases. The article presents possible solutions to improve the design and test technology. Model checking technique can be used for formal verification of specification in design phase. Testing phase can involve independent tester teams.

Słowa kluczowe

EN

design; dependable embedded systems; model checking; temporal logic

PL

projekt; niezawodność systemów wbudowanych; model kontroli

• Wydawca: Komisja Informatyki Polskiej Akademii Nauk, Oddział w Gdańsku
• Czasopismo: Metody Informatyki Stosowanej
• Rocznik: 2010
• Tom: nr 2 (23)
• Strony: 45--51
• Opis fizyczny: Bibliogr. 9 poz., rys., tab.

Twórcy

autor

Grobelna I.

autor

Grobelny M.

• Uniwersytet Zielonogórski, Wydział Elektrotechniki, Informatyki i Telekomunikacji

Bibliografia

• [1] Avizienis A., Laprie J., and Randell B. Fundamental Concepts of Computer System Dependability. IARP/IEEE-RAS Workshop on Robot Dependability: Technological Challenge of Dependable Robots in Human Environments, Seoul, Korea, May 2001
• [2] Clarke E.M., Wing J.M. et al. Formal methods: State of the Art and Future Directions. ACM Computing Surveys, Vol. 28, No. 4, 1996
• [3] Emerson E.A. The Beginning of Model Checking: A Personal Perspective. Lecture Notes in Computer Science, 25 Years of Model Checking: History, Achievements, Perspectives, 2008, pp. 27 – 45
• [4] Huth M., Ryan M. Logic in Computer Science. Modelling and Reasoning about Systems. Cambridge University Press 2004
• [5] Kern C., Greenstreet M.R. Formal Verification in Hardware Design: A Survey. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 4, Issue 2, April 1999, pp. 123 – 193
• [6] Lamport L. “Sometime” is sometimes “not never”. On the Temporal Logic of Programs, Proceedings of the Seventh ACM Symposium on Principles of Programming Languages, ACM SIGACT-SIGPLAN 1980, pp. 174 – 185
• [7] Rice M.V., Vardi M.Y. Branching vs. Linear Time: Final Showdown. Proceedings of the 2001 Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2001, LNCS Volume 2031, Springer-Verlag 2001, pp. 1 – 22
• [8] Schnor B. Dependable and Fault Tolerant Distributed Systems. DAAD-DEDIS Summer Academy, Cottbus 5.9.2008
• [9] Wei-Tek Tsai, Lian Yu, Feng Zhu, Paul R. Rapid embedded system testing using verification patterns. Software, IEEE Volume 22, Issue 4, July-Aug. 2005 pp. 68 – 75