Process and device requirements for mixed-signal integrated circuits in broadband networking

• Autorzy: Iniewski K. , Syrzycki M. , Voinigescu S.P.
• Języki publikacji: EN

Abstrakty

EN

The paper describes the present status of the broadband wireline infrastructure consisting of the backbone core, metre rings, access network, local and storage area networks. Examples of various mixed-signal integrated circuits are described. Based on these considerations required process and device performance is extrapolated.

Słowa kluczowe

EN

CMOS; SiGe; InP; networking; WAN; MAN; SAN; LAN; OEO conversion; cut-off frequency; manufacturability

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2004
• Tom: nr 1
• Strony: 90--98
• Opis fizyczny: Bibliogr. 30 poz., tab., rys.

Twórcy

autor

Iniewski K.

• School of Engineering Science, Simon Frazer University, 8888 University Drive, Burnaby, British Columbia, V5A 1S6, Canada

autor

Syrzycki M.

• Centre for Systems Science, Simon Frazer University, 8888 University Drive, Burnaby, British Columbia, V5A 1S6, Canada

autor

Voinigescu S.P.

• Department of Electrical & Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada

Bibliografia

• [1] L. Cloetens, „Broadband access: the last mile", in Int. Solid-State Circ. Conf., 2001, Paper 1.2.
• [2] R. Ramaswami and K. N. Sivarajan, Optical Networks: A Practical Perspective. Academic Press, 1998.
• [3] N. Alvarez and K. Iniewski, „CMOS FEC: building cost-effective 10 Gbit/s metro networks", Fiberopt. Prod. News, Nov. 2002.
• [4] K. Iniewski, „Dispersion compensation, forward error correction and 10 Gbit/s transponders for metro networks", Lightw. Mag., Jan. 2003.
• [5] A. Banerjee et al., „Generalized multiprotocol label switching: an overview of routing and management enhancements", IEEE Commun. Mag., pp. 144-150, Jan. 2001.
• [6] D. Awduche and Y. Rekhter, „Multiprotocol Lambda switching: combining MPLS traffic engineering control with optical crossconnects", IEEE Commun. Mag., pp. 111-116, Mar. 2001.
• [7] K. Iniewski, „OEO conversion still a fact of life in telecom nets", Lightwave, May 2002.
• [8] T. Ellermeyer et al., „A 10 Gbit/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver", J. Solid-State Circ., vol. 35, pp. 1958-1963, 2000.
• [9] A. Neukermans et al., „MEMS technology for optical networking applications", IEEE Commun. Mag., pp. 63-69, Jan. 2001.
• [10] N. McKeown, M. Izzard, A. Mekkittikul, B. Ellersick, and M. Horowitz, „The tiny tera: a packet switch core", in Hot Interconnects V, Stanford University, Aug. 1996 (also: IEEE Micro, pp. 26-33, Jan./Feb. 1997).
• [11] N. McKeown, „The iSLIP scheduling algorithm for input-queued switches", IEEE/ACM Trans. Net., vol. 7, pp. 188-201, 1999.
• [12] W. Bux et al., „Technologies and building blocks for fast packet forwarding", IEEE Commun. Mag., pp. 70-77, Jan. 2001.
• [13] U. Black, Emerging Communication Technologies. Prentice Hall, 1997.
• [14] J. Savoj and B. Rezavi, „A 10 Gbit/s CMOS clock and data recovery circuit with frequency detection", in Int. Solid-State Circ. Conf., 2001, Paper 5.3.
• [15] M. Reinhold et al., „40 Gbit/s clock and data recovery/1:4 DEMUX IC in SiGe technology", in Int. Solid-State Circ. Conf., 2001, Paper 5.6.
• [16] R. He et al., „A DSP based receiver for 1000 BASE-T PHY", in Int. Solid-State Circ. Conf., 2001, Paper 19.6.
• [17] A. Gattani et al., „A CMOS HDSL2 analog front-end", J. Solid-State Circ., vol. 35, pp. 1964-1975, 2000.
• [18] P. Laaser et al., „A 285 mW CMOS single chip analog front end for G.SHDSL", in Int. Solid-State Circ. Conf., 2001, Paper 19.1.
• [19] S. Voinigescu, P. Popescu, P. Banens, M. Copeland, G. Fortier, K. Howlett, M. Herod, D. Marchesan, J. Showell, S. Szilagyi, H. Tran, and J. Weng, „Circuits and technologies for highly integrated optical networking IC's at 10 Gbit/s and 40 Gbit/s", in Proc. IEEE CICC, 2001, pp. 331-338.
• [20] S. P. Voinigescu, D. S. Mc.Pherson, F. Pera, S. Szilagyi, M. Tazlauanu, and H. Tran, „A comparison of silicon and III-V technology performance and building block implementations for 10 and 40 Gbit/s optical networking ICs", Int. J. High Speed Electron. Syst., vol. 13, no. 1, 2003.
• [21] E. Sano, „High-speed lightwave communication ICs based on III-V compound semiconductors", IEEE Commun. Mag., pp. 154-158, Jan. 2001.
• [22] M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. Regolini, D. Dutarte, P. Ribot, D. Lenoble, R. Pantel, and S. Monfray, „Silicon-on-nothing (SON) - an innovative process for advanced CMOS", IEEE Trans. Electron Dev., vol. 47, p. 2179, 2000.
• [23] W. Maly, „Modeling of lithography related yield losses for CAD of VLSI", IEEE Trans. CAD, vol. CAD-4, no. 3, pp. 166-177, 1985.
• [24] S. W. Director, W. Maly, and A. Strojwas, VLSI Design for Manufacturing: Yield Enhancement. Boston: Kluwer, 1989.
• [25] H. T. Heineken, J. Khare, and M. d'Abreau, „Manufacturability analysis of standard cell libraries", in Proc. IEEE Custom ICs Conf., 1998, pp. 321-324.
• [26] D. H. M. Walker, Yield Simulation for Integrated Circuits. Kluwer, 1987.
• [27] R. Ockey and M. Syrzycki, „Analysis of manufacturability factors for analog CMOS A/D converter building blocks", Analog Integr. Circ. Sig. Proc. Int. J., Kluwer, vol. 26, no. 3, pp. 239-255, 2001.
• [28] U. Gatti, F. Maloberti, and V. Liberali, „Full stacked layout of analogue cells", in Proc. IEEE Int. Symp. Circ. Syst., 1989, pp. 1123-1126.
• [29] R. Naiknaware and T. S. Fiez, „Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching consideration", IEEE J. Solid-State Circ., vol. 34, no. 3, pp. 304-316, 1999.
• [30] P. Khademsameni and M. Syrzycki, „Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions", in Proc.17th IEEE Int. Symp. Def. Fault Toler. VLSI Syst., Vancouver, Canada, 2002, pp. 3-11.