Closed-form 2D modeling of sub-100 nm MOSFETs in the subthreshold regime

• Autorzy: Osthaug J. , Fjeldly T.A. , Iniguez B.
• Języki publikacji: EN

Abstrakty

EN

Closed-form 2D modeling of deep-submicron and sub-100 nm MOSFETs is explored using a conformal mapping technique where the 2D Poisson equation in the depletion regions is separated into a 1D long-channel case and a 2D Laplace equation. The 1D solution defines the boundary potential values for the Laplacian, which in turn provides a 2D correction of the channel potential. The model has been tested for classical MOSFETs with gate lengths in the range 200-250 nm, and for a super-steep retrograde MOSFET with a gate length of 70 nm. With a minimal parameter set, the present modeling reproduces both qualitatively and quantitatively the experimental data obtained for such devices.

Słowa kluczowe

EN

sub-100 nm MOSFET; two-dimensional device modeling; conformal mapping; threshold voltage; subthreshold regime; leakage current

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2004
• Tom: nr 1
• Strony: 70--79
• Opis fizyczny: Bibliogr. 21 poz., rys.

Twórcy

autor

Osthaug J.

• UniK - University Graduate Center, N-2027 Kjeller, Norway

autor

Fjeldly T.A.

• UniK - University Graduate Center, N-2027 Kjeller, Norway

autor

Iniguez B.

• Universitat Rovira i Virgili (URV), Tarragona, E-43001, Spain

Bibliografia

• [1] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide. Boston: Kluwer, 1999.
• [2] W. Liu and C. Hu, „BSIM3V3 MOSFET model", in Silicon and Beyond: Advanced Device Models for Circuit Simulators, M. S. Shur and T. A. Fjeldly, Eds. Singapore: World Scientific, 2000, pp. 1-31.
• [3] W. Liu et al., BSIM4 User's Manual. Berkeley: University of California, 2000.
• [4] T. Ytterdal, Y. Cheng, and T. A. Fjeldly, Device Modeling for Analog and RF CMOS Circuit Design. London: Wiley, 2003.
• [5] C. Enz, F. Krummenacher, and E. A. Vittoz, „An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications", in Analog Integrated Circuits and Signal Processing. Boston: Kluwer, 1995, vol. 8, pp. 83-114.
• [6] R. Velghe, D. Klaassen, and F. Klaassen, „MOS Model 9". Unclassified Report NL-UR 003/94, Philips Electronics N.V, 1994.
• [7] K. Lee, M. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI. Englewood Cliffs, NJ: Prentice Hall, 1993.
• [8] T. A. Fjeldly, T. Ytterdal, and M. Shur, Introduction to Device Modeling and Circuit Simulation. New York: Wiley, 1998.
• [9] ITRS - International Technology Roadmap for Semiconductor. Austin: Semiconductor Industry Assoc., 2001.
• [10] K. N. Ratnakumar and J. D. Meindl, „Short-channel MOSFET threshold voltage model", IEEE J. Solid-State Circ., vol. 17, pp. 937-948, 1982.
• [11] Y. A. El-Mansy and A. R. Boothroyd, „A simple two-dimensional model for IGFET operation in the saturation region", IEEE Trans. Electron Dev., vol. 40, pp. 254-262, 1977.
• [12] V. K. De and J. D. Meindl, „An analytical threshold voltage and subthershold current model for short-channel MESFETs", IEEE J. Solid-State Circ., vol. 28, pp. 169-172, 1993.
• [13] S.-H. Oh, D. Monroe, and J. M. Hergenrother, „Analytic description of short-channel effects in fully-depleted double gate and cylindrical, surrounding-gate MOSFETs", IEEE Electron Dev. Lett., vol. 21, no. 9, 2000.
• [14] Y.-S. Pang and J. R. Brews, „Analytical subthreshold surface potential model for pocket n-MOSFETs", IEEE Trans. Electron Dev., vol. 49, pp. 2209-2216, 2002.
• [15] A. Klös and A. Kostka, „A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling", Solid-State Electron., vol. 39, pp. 1761-1775, 1996.
• [16] E. Weber, Electromagnetic Fields, vol. 1: Mapping of Fields. New York: Wiley, 1950.
• [17] P. M. Zeitzoff, J. A. Huchby, and H. R. Huff, „MOSFET and frontend process integration: scaling trends, challenges, and potential solutions through the end of the roadmap", in Int. J. High Speed Electron. Syst., 2002, vol. 12, pp. 267-293.
• [18] T. A. Fjeldly, B. J. Moon, and M. S. Shur, „Approximate analytical solution of the generalized diode equation", IEEE Trans. Electron Dev., vol. 38, pp. 1976-1977, 1991.
• [19] T. A. Fjeldly and M. S. Shur, „Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs", IEEE Trans. Electron Dev., vol. 40, pp. 137-145, 1993.
• [20] J. E. Chung, M.-C. Jeng, J. E. Moon, P.-K. Ko, and C. Hu, „Performance and reliability design issues for deep-submicrometer MOSFET's", IEEE Trans. Electron Dev., vol. 38, no. 3, pp. 545-554, 1991.
• [21] Q. Xu, H. Qian, H. Yin, H. Ji, B. Chen, Y. Zhu, M. Liu, Z. Han, H. Hu, Y. Qiu, and D. Wu, „The investigation of key technologies for sub-0.1-mm CMOS device fabrication", IEEE Trans. Electron Dev., vol. 48, no. 7, 2001.