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Tytuł artykułu

Silicon microelectronics: where we have come from and where we are heading

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The paper briefly presents the history of microelectronics and the limitations of its further progress, as well as possible solutions. The discussion includes the consequences of the reduction of gate-stack capacitance and difficulties associated with supply-voltage scaling, minimization of parasitic resistance, increased channel doping and small size. Novel device architectures (e.g. SON, double-gate transistor) and the advantages of silicon-germanium are considered, too.
Słowa kluczowe
EN
MOSFET   scaling   SiGe   SOI  
Rocznik
Tom
Strony
7--14
Opis fizyczny
Bibliogr. 29 poz., tab., rys.
Twórcy
autor
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa st 75, 00-662 Warsaw
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa st 75, 00-662 Warsaw
autor
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa st 75, 00-662 Warsaw
Bibliografia
  • [1] D. Kahng and M. M. Atalla, "Silicon-silicon dioxide field induced surface devices", in IREE Solid-State Dev. Res. Conf., Pittsburgh, USA, 1960.
  • [2] J. E. Lilienfeld, "Method and apparatus for controlling electric currents", US patent, no. 1 745 175, 1930.
  • [3] C. Shannon, "A mathematical theory of communication", Bell Syst. Techn. J., vol. 27, July 1948.
  • [4] J. Szabatin, "Era informacyjna a teoria Shannona", Przegląd Telekomunikacyjny, no. 4, pp. 278-287, 2000 (in Polish).
  • [5] G. E. Moore, "Cramming more components onto integrated circuits", Electronics, vol. 38, 1965.
  • [6] N. Negroponte, Being Digital. Alfred Knopf, 1995.
  • [7] G. Gilder, Telecosm: How Infinite Bandwidth will Revolutionize the World. Free Press, 2000.
  • [8] J. D. Plummer and P. B. Griffin, "Material and process limits in silicon VLSI technology", Proc. IEEE, vol. 89, pp. 240-257, 2001.
  • [9] A. Jakubowski and L. Łukasiak, "O telekomunikacyjnych pożytkach z elektroniki wynikających", Przegl¡d Telekomunikacyjny, no. 1, pp. 5-11, 2003 (in Polish).
  • [10] C. T. Liu, "Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs", IEDM Tech. Dig., pp. 747-750, 1998.
  • [11] H. S. Momose et al., „Tunneling gate oxide approach to ultrahigh current drive in small-geometry MOSFETs", IEDM Tech. Dig., pp. 593-596, 1994.
  • [12] T. Skotnicki, „Heading for decananometer CMOS - is navigation among icebergs still a viable strategy?", in 30th Eur. Solid-State Dev. Res. Conf., Cork, Ireland, 2000.
  • [13] H. Iwai and H. S. Momose, „Ultra-thin gate oxides - performance and reliability", IEDM Tech. Dig., pp. 163-166, 1998.
  • [14] B. E. Weir et al., „Ultra-thin gate dielectric: they break down, but do they fail?", IEDM Tech. Dig., pp. 73-76, 1997.
  • [15] J. H. Stathis and D. J. DiMaria, „Reliability projection for ultra-thin oxides at low voltage", IEDM Tech. Dig., pp. 167-170, 1998.
  • [16] G. Groeseneken et al., „Reliability of ultra-thin oxides for the gigabit generations", in 29th Eur. Solid-State Dev. Res. Conf., Leuven, Belgium, 1999, p. 72.
  • [17] A. M. Stoneham and C. J. Sofield, „Modeling the oxide and the oxidation process: can silicon oxidation be solved?", in Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, E. Garfunkel et al., Eds. Kluwer, 1998.
  • [18] L. C. Feldman et al., „Ultrathin dielectrics in silicon microelectronics - an overview", in Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, E. Garfunkel et al., Eds. Kluwer, 1998.
  • [19] H. Iwai and S. Ohmi, „CMOS downsizing and high-k gate insulator technology", in 4th IEEE Int. Caracas Conf. Dev., Circ. Syst. ICCDCS'2002, pp. D049-1-D049-8.
  • [20] H.-S. P. Wong, „Beyond the conventional transistor", IBM J. Res. Dev., vol. 46, no. 2/3, 2002.
  • [21] J. R. Brews, W. Fichtner, E. Nicollian, and S. M. Sze, „Generalized guide for MOSFET miniaturization", IEEE Electron. Dev. Lett., vol. EDL-1, pp. 2-4, 1980.
  • [22] R. W. Keyes, „Fundamental limits of silicon technology", IEEE Proc., vol. 89, pp. 227-239, 2001.
  • [23] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer, 1995.
  • [24] A. Jakubowski, M. Jurczak, and L. Łukasiak, „Krzem na izolatorze - przyrządy", Elektronika, vol. 37, no. 4, pp. 15-20, 1996 (in Polish).
  • [25] T. Skotnicki, S. Monfray, and C. Fenouillet-Beranger, „Emerging silicon-on-nothing (SON) devices technology", in Proc. Int. Symp. SOI Technol. Dev. XI, Electrochem. Soc. Proc., vol. 2003-05, pp. 133-148, 2003.
  • [26] S. Monfray and T. Skotnicki et al., „First 80 nm SON (siliconon-nothing) MOSFETs with perfect morphology and high electrical performance", IEDM Tech. Dig., pp. 645-648, 2001.
  • [27] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, „Device scaling limits of Si MOSFETs and their application dependencies", IEEE Proc., vol. 89, pp. 259-288, 2001.
  • [28] J.-S. Rieh et al., „SiGe HBTs with cut-off frequency of 350 GHz", IEDM Tech. Dig., pp. 771-774, 2002.
  • [29] B. Doris et al., „Extreme scaling with ultra-thin SOI channel MOSFETs", IEDM Tech. Dig., pp. 267-270, 2002.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPS2-0027-0030
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