Characterization of SOI fabrication process using gated-diode measurements and TEM studies

• Autorzy: Gibki J. , Kątcki J. , Ratajczak J. , Łukasik L. , Jakubowski A. , Tomaszewski D.
• Języki publikacji: EN

Abstrakty

EN

SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.

Słowa kluczowe

EN

microelectronics; SOI technology; characterization

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2000
• Tom: nr 3-4
• Strony: 81--83
• Opis fizyczny: Bibliogr. 5 poz., tab., rys.

Twórcy

autor

Gibki J.

autor

Kątcki J.

autor

Ratajczak J.

autor

Łukasik L.

autor

Jakubowski A.

autor

Tomaszewski D.

• Institute of Microelectronics and Optoelectronics, Warsaw University of Technology