Optimized RTL design and impiementation of LZW algorithm for high bandwidth applications

• Autorzy: Naqvi S. , Naqvi R. , Riaz R. A. , Siddiqui F.

Warianty tytułu

PL

Optymalizowany układ RTL i algorytm LZW w zastosowaniach szerokopasmowych

• Języki publikacji: EN

Abstrakty

EN

This paper presents a high-speed low-complexity Register Transfer Logic (RTL) design and impiementation of the Iossiess Lempel-Ziv-Welch (LZW) algorithm on Xilinx Virtex II device family for High Bandwidth Applications. Comparative analysis of the proposed design with the established commercial data compression and decompression accelerators show that the proposed design offers comparatively high throughput 1.42 Gbits/s, elevated throughput/slice value 151.8 Kbytes/s/slice and Iower operational power requirements 333 mW.

PL

W artykule zaprezentowano nieskomplikowany, wysokiej częstotliwości projekt obwodu RTL oraz bezstratny algorytm LZW z układem Xilinx Virtex II. Porównano zaproponowany układ z komercyjnymi układami kompresji i stwierdzono, że umożliwia on przepustowość 1.42 Gbit/s przy poborze mocy 333 mW.

Słowa kluczowe

EN

lossless compression; Lempel-Ziv-Welch; LUTs and Throughput/Slice

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2011
• Tom: R. 87, nr 4
• Strony: 279--285
• Opis fizyczny: Bibliogr. 19 poz., rys., tab.

Twórcy

autor

Naqvi S.

autor

Naqvi R.

autor

Riaz R. A.

autor

Siddiqui F.

• COMSATS Pakistan,

Bibliografia

• [1] M.-B. Lin, J.-F. Lee, G. E. Jan, A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems., 14(2006), 925-936.
• [2] M. -B. Lin, Y. -Y. Chang, A New Architecture of a Two-Stage Lossless Data Compression and Decompression Algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems., 17(2009), 1297-1303.
• [3] M. -B. Lin, Y. -Y. Chang, A universal algorithm for sequential data compression, IEEE Transactions on Information Theory., 23(1977), 337-343.
• [4] T. H. Cormen, C. E. Leiserson, R. L Rivest, C. Stein, Introduction to Algorithms (TMcGraw-Hill, 2001).
• [5] R. Gallager, Variations on a theme by Huffman, IEEE Transactions on Information Theory., 24(1978), 668 - 674.
• [6] N. Ranganathan, S. Henriques, High-speed VLSI designs for Lempel-Ziv-based data compression, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing., 40(1993), 96-106.
• [7] I. H. Witten, R. M. Neal, J. G. Cleary, T.A. Welch, A Technique for High-Performance Data Compression, Computer., 17(1984), 08-19.
• [8] M.A. Bassiouni, Data Compression in Scientific and Statistical Databases, IEEE Transactions on Software Engineering, vol. SE-II, pp: 1047-1058, 1985.
• [9] M.A. Bassiouni, A. Mukherjee, N. Ranganathan, Enhancing arithmetic and tree-based coding, Inf. Process. Manage., 25(1989), 293-305.
• [10] R. C. Gonzalez, R. E. Woods, Digital Image Processing (Addision-Welsley, 1992).
• [11] S. Bunton, G. Borriello, Practical dictionary management for hardware data compression, Communication ACM., 35(1992), 95-104.
• [12] J. A. Storer, Data Compression: Methods and Theory, (Rockville, MD: Computer Science Press, 1988).
• [13] J. A. Storer, T.G. Szymanski, Data compression via textual substitution, J. ACM., 29(1982), 928-951.
• [14] R. A. Wagner, Common phrases and minimum-space text storage, Communication ACM., 16(1973), 148-152.
• [15] J. L. Nunez, S.Jones, Gbit/s lossless data compression hardware, IEEE Transactions on Very Large Scale Integration (VLSI) Systems., 11(2003), 499-510.
• [16] T. A. Welch, A Technique for High-Performance Data Compression, Computer, 17(1984), 08-19.
• [17] Wei Cui, "New LZW Data Compression Algorithm and Its FPGA Implementation", Picture Coding Symposium., ISBN: 978-989-8109-05-7, (Suvisoft, Portugal, 2007).
• [18] LZRW3, Data Compression Core for Xilinx FPGA, (Helion Technology, England 2006).
• [19] Enhanced Lossless Data Compression (ELDC-3) IP-Core, (GEMAC mbH, Germany, Nov 4, 2007).