FPGA realization of the high-speed residue-to-binary converter based on the Chinese Remainder Theorem

• Autorzy: Czyżak M. , Smyk R.
• Konferencja: Computer Applications in Electrical Engineering 2010 [Poznań, April 19-21, 2010]
• Języki publikacji: EN

Abstrakty

EN

An architecture and the FPGA realization of a high-speed residue-to-binary converter for five-bit moduli are presented. The converter algorithm is based on the Chinese Remainder Theorem. The orthogonal projections are obtained by the look-up. The modulo M summation of projections is carried out by using the tree of carry-save adders with the succesive reduction of the sum to 2M range. Succesively the segmentation of the output vectors of the carry-save adder and final modulo M reduction are performed.

Słowa kluczowe

EN

Chinese remainder theorem; FPGA realization; converter algorithm; converter architecture

PL

chińskie twierdzenie o resztach; konwerter

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2010
• Tom: No. 63
• Strony: 197--203
• Opis fizyczny: Bibliogr. 7 poz.

Twórcy

autor

Czyżak M.

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

• [1] Szabo N.S., Tanaka R.J., Residue Arithmetic and its Applications to Computer Technology, New York, McGraw-Hill, 1967.
• [2] Soderstrand M.A. et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, NY, 1986.
• [3] Elleithy K.M., Bayoumi M.A.: Fast and flexible architectures for RNS arithmetic decoding, IEEE Trans, on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, No. 4, April 1992, pp. 226-235.
• [4] Piestrak S.J.: Design of high-speed residue-to-binary number system converter based on the Chinese Remainder Theorem, Proc. ICCD'94, Int. Conf. on Computer Design: VLSI in Computers and Processors, Cambridge, MA, Oct. 10-12, 1994, pp. 508-511.
• [5] Cardarilli G.C., Re M., Lojacono R., A systolic architecture for high-performance scaled residue to binary conversion, IEEE Trans. Circuits Syst.-I :Fundamental Theory and Applications, vol. 47, October 2000, pp.667-669.
• [6] Czyżak M., High-speed residue-to-binary converter based on Chinese Remainder Theorem, Proc. of the Sixth Int. Sci. Conf. Electronic Computers and Informatics, ECI’2004. Sept. 22-24, 2004, Kosice-Herl'any, Slovakia, pp. 212-217.
• [7] Czyżak M., An improved high-speed residue-to-binary converter based on Chinese Remainder Theorem, Pomiary Automatyka Kontrola, vol. 53, no. 4, 2007, pp. 72-75.