High-speed FPGA pipelined binary-to-residue converter

• Autorzy: Czyżak M. , Smyk R.
• Konferencja: Scientific Conference on Computer Applications in Electrical Engineering [13; April 14-16, 2008; Poznan]
• Języki publikacji: EN

Abstrakty

EN

An architecture and the FPGA realization of a high-speed pipelined binary-to-residue converter for five-bit moduli are presented. The converter algorithm is based on segmentation of the input binary word into segments of at most five-bit length. For the number represented by each segment modulo m reduction is performed. The obtained residues are added by using the multi-operand modulo adder m based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to 2m range and fast two-operand modulo m adder.

Słowa kluczowe

EN

binary-to-residue converter; residue number system; converter architecture; FPGA

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2008
• Tom: No 58
• Strony: 65--72
• Opis fizyczny: Bibliogr. 10 poz.

Twórcy

autor

Czyżak M.

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

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• [8] A.B. Premkumar," Improved memoryless RNS forward converter based on periodicity of residues," IEEE Trans. Circuits and Systems-II, Express Briefs, vol. 53, no.2, Feb.2006, pp. 133-137.
• [9] A. Avizienis, "Arithmetic codes: cost and effectiveness studies for application in the didgital system design," IEEE transactions on Computers, vol. C-20, pp. 1322-1331, Nov. 1971.
• [10] S.J. Piestrak, "Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem, " Proc. ICCD'94, Int.Conf. on Computer Design: VLSI in Computers and Processors, Cambridge, MA, Oct. 10-12, 1994, pp. 508-511.