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High-speed FPGA pipelined binary-to-residue converter

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Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
Konferencja
Scientific Conference on Computer Applications in Electrical Engineering [13; April 14-16, 2008; Poznan]
Języki publikacji
EN
Abstrakty
EN
An architecture and the FPGA realization of a high-speed pipelined binary-to-residue converter for five-bit moduli are presented. The converter algorithm is based on segmentation of the input binary word into segments of at most five-bit length. For the number represented by each segment modulo m reduction is performed. The obtained residues are added by using the multi-operand modulo adder m based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to 2m range and fast two-operand modulo m adder.
Rocznik
Tom
Strony
65--72
Opis fizyczny
Bibliogr. 10 poz.
Twórcy
autor
autor
  • Gdansk University of Technology
Bibliografia
  • [1] N.S. Szabo and R.J. Tanaka, Residue Arithmetic and its Applications to Computer Technology, New York, McGraw-Hill, 1967.
  • [2] M .Soderstrand et al., Residue Number System Arithmetic. Modern Applications in Digital Signal Processing, IEEE Press, NY, 1986.
  • [3] A. Omondi, B. Premkumar, Residue Number Systems: Theory and Implementation, London, Imperial College Press, 2007.
  • [4] G. Alia, E. Martinelli, "VLSI binary-residue converters for pipelined processing," Computer J., vol. 33, no.5, pp. 473-475, 1990.
  • [5] S.J.Piestrak, "Design of residue generators and multioperand modulo adders using carry-save adders," IEEE Trans. Comp., vol. 43, pp.68-77, Jan. 1994.
  • [6] A.B. Premkumar," A formal framework for conversion from binary to residue numbers," IEEE Trans. Circuits and Systems-II, vol.49, no.2, Feb.2002, pp. 135-144.
  • [7] M. Czyżak, "High-speed binary-to-residue converter with improved architecture," 27th Int. Conf. on Fundamentals of Electrotechnics and Circuit Theory, Gliwice-Niedzica, May 26-29, 2004, pp. 431-436.
  • [8] A.B. Premkumar," Improved memoryless RNS forward converter based on periodicity of residues," IEEE Trans. Circuits and Systems-II, Express Briefs, vol. 53, no.2, Feb.2006, pp. 133-137.
  • [9] A. Avizienis, "Arithmetic codes: cost and effectiveness studies for application in the didgital system design," IEEE transactions on Computers, vol. C-20, pp. 1322-1331, Nov. 1971.
  • [10] S.J. Piestrak, "Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem, " Proc. ICCD'94, Int.Conf. on Computer Design: VLSI in Computers and Processors, Cambridge, MA, Oct. 10-12, 1994, pp. 508-511.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPP1-0092-0018
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