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High-speed FPGA pipelined binary-to-residue converter

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Warianty tytułu
Scientific Conference on Computer Applications in Electrical Engineering [13; April 14-16, 2008; Poznan]
Języki publikacji
An architecture and the FPGA realization of a high-speed pipelined binary-to-residue converter for five-bit moduli are presented. The converter algorithm is based on segmentation of the input binary word into segments of at most five-bit length. For the number represented by each segment modulo m reduction is performed. The obtained residues are added by using the multi-operand modulo adder m based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to 2m range and fast two-operand modulo m adder.
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Bibliogr. 10 poz.
  • Gdansk University of Technology
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