Tranzystor - 60 lat minęło i co dalej?

Jakubowski, A.; Łukasiak, L.

Artykuł - szczegóły

Tytuł artykułu

Tranzystor - 60 lat minęło i co dalej?

Autorzy

Jakubowski A. , Łukasiak L.

Identyfikatory

Warianty tytułu

Transistor is 60 years old - what's next?

Języki publikacji

Abstrakty

Przedstawiono historię elektroniki półprzewodnikowej ze szczególnym uwzględnieniem tranzystora MOS, trudności związane z dalszą miniaturyzacją, możliwe kierunki rozwoju oraz wybrane ograniczenia fundamentalne.

The papers briefly presents the history of semiconductor electronics with emphasis on MOS transistor, difficulties associated with further miniaturization, possibile directions of development and selected fundamental limitations.

Słowa kluczowe

skalowanie SOI tranzystor bipolarny tranzystor MOS

SOI bipolar transistor MOSFET scaling

Wydawca

Wydawnictwo SIGMA-NOT

Czasopismo

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

Rocznik

2008

Tom

R. 81, nr 5

Strony

666--671

Opis fizyczny

Bibliogr. 41 poz., rys., tab., wykr.

Twórcy

autor

Jakubowski A.

autor

Łukasiak L.

Instytut Mikroelektroniki i Optoelektroniki, Politechnika Warszawska, A.Jakubowski@imio.pw.edu.pl

Bibliografia

[1] Lilienfeld J. E.: Device for controlling electric current, U. S. patent 1 900 018. Application filed Mar. 28,1928, granted Mar. 7,1933
[2] Wilson A. H: Thetheoryofelectronicserriconductors, I', Proc. Roy. Soc., vol. A133,1931
[3] Wilson A. H: Tr&theoryofelectrmicsemiconductors, II', Proc. Roy. Soc., vol. A134,1931
[4] Dawidow B.: On the rectification of current at the boundary between two semiconductors, Compt. Rend.. (Doki.) Acad. Sci. USSR, vol. 20, pp. 279-282, 1938
[5] DawidowB:.Onthetheoryofsolidrectifiers,Compt. Rend.. (Doki.) Acad.Sci. USSR,vol.20,1938
[6] Bethe H. A, MIT Radiation Laboratory Report no. 43/12,1942
[7] Riordan M., Hoddeson L, Herring C, The invention of the transistor, Reviews of Modern Physics, vol. 71, no. 2,1999
[8] Łojek B.: History of semiconductor engineering, Springer, New York,2007.
[9] Ross I. M.: Thelnventionofthe Transistor, Proc. IEEE, vol. 86, no. 1., Jan. 1998
[10] PierceJ. R.: TheNamingofthe Transistor, Proc. IEEE, vol. 86, no 1., 1998
[11] Dennard R. K, Gaensslen F H, Yu H. -N„ RideoutV L, Basous E„ Le-Blanc A. R.: Design of ion-implanted MOSFETs with very smali physical dimensions, IEEE J. Solid-State Circuits., vol. 9,1974
[12] Sah C. -I: Evolution of the MOS transistor - from conception to VLSI,Proc. IEEE, vol. 76, 1988
[13] M. M. Atalla, M. Tanenbaum, E. J. Sheibner, Stabilization ofsilicon surface by thermally grown oxides, Bell Syst. Tech. J., vol. 38,1959
[14] Kahng D., Atalla M. M.: Silicon-silicon dioxide field induced surface devices, presented at the IRE-AIEE Solid-State Device Research Conference at Carnegie Institute of Technology, Pittsburgh, USA., 1960
[15] Wanlass F M., Sah C. T: Nanowatt logie using field-effect metal-oxide semiconductor triodes, in Technical Digest of the IEEE 1963, Int. Solid--State Circuit Conf., February 20,1963
[16] FairR. B.: History of some earfy developments in ion-implantation technology leading to silicon transistor manufacturing, Proc. IEEE, vol. 86,no. 1,1998
[17] Kerwin R. E, Klein D. L.,. Sarace J. C: Method for making MIS structu-res, U. S. Patent 3 475 234, filed Mar. 27,1967, issued Oct. 28,1969
[18] Mohizuki T, Shibata K., Inoue T, Obuchi K., Kashiwogi M.: A newgate materiał for MOS devices - molybdenum silicide (MoSiZ) ECS Extended Abstracts, vol, 1977
[19] Saraswat K. C, Mohammedi F, Meindl J. D.: WSi2 gate MOS devices, lEDMTech. Dig.,1979.
[20] Crowder B., Zirinsky S.: 1 pm VLSI MOSFET technology: Part VII -Metal interconnection silicide technology - a futurę perspective, IEEE Trans. Electron Dev., vol. 26, 1979.
[21] Hunter W R., Holloway T C, Chatterjee P K., Tasch A. F, New adgedefined verbcaletch approaches for submicrometer MOSFET fabrication, lEDMTech. Dig., 1980.
[22] Wong S. S., Bradbury D. R., Chen D. C, Chiu K. Y: Elevated source/ drain MOSFET, IEDM Tech. Dig., 1984
[23] Mohizuki T , Wise K. D.: An n-channel MOSFET with Schottky source and drain, IEEE Electron Dev. Lett., vol. 5,1984
[24] Ghani T, Mistry K. Packan P, Thompson S., Stettler M., Tyagi S, Bohr M.: Scaling challenges and dewce design requirements for high performance sub-50 nm gate length planar CMOS transistors, Symp. VLSI Technology Dig. Tech. Papers, 2000
[25] OguraS., CodellaC. F, Rovedo N„ Shepard J. F, RisemanS.Ahalfmicron MOSFET using double implanted LDD, IEDM Tech. Dig., 1982
[26] Tian H, Hulfachor R. B., Ellis-Monaghan J. J., Kim K. W, Littlejohn M. A., Hauser J. R., Masnar N. A.: An evaluation of super-steep-retrograde channel doping for deepsubrncron MOSFT applications, IEEE Trans. Electron Dev„ vol. 41,1994
[27] Chuang C. -T, Bernstein K., Joshi R. V, Puri R., Kim K, Nowak E. J., Ludwig T, Aller I.: Focusing on planar device structures and strainedsilicon for handling silicon scaling issues in the deep sub-100 nm regime, IEEE Circuits & Devices Magazine, Jan. /Feb. 2004
[28] Zeitzoff P M, Chung J. E.: A perspecłive from the 2003 ITRS, IEEE Circuits & Dewces Magazine, Jan/Feb 2005
[29] Lundstrom M., Ren Z., Essential physiesof carrier transport in nanoscale MOSFETs, IEEE Trans. Electron Dev., vol. 49, 2002
[30] Moore G. E. Progress in digital integrated electronics, IEEE Int. Dev. Meeting, Dig. 1975
[31] Kurzweil R.: The singularity is near, Penguin Books, 2005
[32] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2007
[33] Wong H. -S. R: Beyond the conventional transistor, Solid-State Electron., vol. 49, 2005
[34] Collinge J. -R: Silicon-on-lnsulator technology: materials to VLSI, Nuwer Academic Publishers, 2004
[35] Skotnicki T, Hutchby J. A, King T -J., Wong H. -S. R, Boeuf E:Theend of CMOS scaling, IEEE Circuits & Devices Magazine, Jan. /Feb. 2005.
[36] Colinge J. R: Multiple gate SO/ MOSFETs, Solid-State Electron., vol. 48, 2004
[37] Nowak E. J„ Aller I., Ludwig T, Kim K., Joshi R. V, Chuang C,-T, Bernstein K., Puri R.: Tuming silicon on its edge, IEEE Orcurts & Dewces Magazine, Jan/Feb 2004
[38] Mohta N., Thompson S. E.: Mobility enhancemen, IEEE Circuits and Devices Magazine, Sept/Oct, 2005
[39] Lloyd S.: Ultimatephysicallimits to computation, Nature, vol. 406,2000
[40] Izydorczyk J.: Prawo Moore i granice rozwoju technologii elektronowej, Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne, nr 2-3, 2007
[41] Zhirnov W, Cavin R. K, Hutchby J. A„ Bourianoff G. I.: Limits to Dinary logie switch scaling - a gedanken model, Proc. IEEE, vol. 91,2003

Typ dokumentu

Bibliografia

Identyfikator YADDA

bwmeta1.element.baztech-article-BPOM-0005-0007