An FPGA-based implementation of ADALINE neural network with low resource utilization and fast convergence

• Autorzy: Tehrani O. , Ashourian M.

Warianty tytułu

PL

Sieć neuronowa typu FPGA ADALINE o szybkiej zbieżności i małym zużyciu zasobów

• Języki publikacji: EN

Abstrakty

EN

n FPGA-based fixed-point ADALINE Neural Network core with low resource utilization and fast convergence speed is proposed for embedded adaptive signal processing in real-time. The core is designed in VHDL93 language and is FPGA-brand-independent so can be embedded on any brand to create a system-on-programmable-chip (SoPC).

PL

Zaproponowano wykorzystanie sieci neuronowej typu FPGA ADALINE do przetwarzania sygnału w czasie rzeczywistym. Rdzeń jest zaprojektowany przy użyciu języka VHDL93. Narzędzie może być wbudowane w dowolny obwód w tym także typu system-on-programmable-chip (SoPC).

Słowa kluczowe

EN

ADALINE Neural Network; adaptive signal processing; FPGA Core; SoPC

PL

sieć neuronowa; adaptacyjne przetwarzanie sygnałów

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2010
• Tom: R. 86, nr 12
• Strony: 288--292
• Opis fizyczny: Bibliogr. 14 poz., rys., tab.

Twórcy

autor

Tehrani O.

autor

Ashourian M.

• Islamic Azad University-Najafabad Branch,

Bibliografia

• [1] S.M. Kuo and D.R. Morgan, Active Noise Control: A Tutorial Review, IEEE Proceeding, vol. 78, 1999, pp. 943-973.
• [2] K.S. Chaitanya, P. Muralidhar and C.C. Rama Rao, Implementation of reconfigurable adaptive filtering algorithms, International Conference on SIGNAL PROCESSING SYSTEMS, 2009.
• [3] Tyseer Aboulnasr, A robust Variable Step-Size LMS-Type Algorithm: Analysis and Simulations, IEEE Transaction on Signal Processing, 45 (3), 1997, pp. 631-639.
• [4] Wee-Peng and B. Farhang-Boroujeny, A New Class of Gradient Adaptive Step-Size LMS Algorithm, IEEE Transaction on Signal Processing, 49(4), 2001, pp. 805-810.
• [5] Katsushige Matsubara and Kiyoshi Nishikawa, A new pipelined architecture of the LMS algorithm without degradation of convergence characteristics, IEEE ICASSP Conference, 5(4), 1997, PP.4125-4128.
• [6] HU Zheng-wei and Xie Zhi-yuan, Application of Pipeline Technique In Realization of LMS Algorithm, Journal of North China Electric Power University, 31(3), 2004, pp. 93-96.
• [7] S. Haykin, Adaptive Filter Theory (Prentice Hall, Upper Saddle River, NJ, 2002).
• [8] M. Tarrab and A. Feuert, Convergence and Performance Analysis of the normalized LMS Algorithm with Uncorrelated Gaussian Data, IEEE Transaction on Inform. Theory, 34, (4), 1988, pp. 680-691.
• [9] A.I. Sulyman and A. Zerguine. “Echo cancellation using a variable step-size NLMS algorithm”, SIGNAL PROCESSING Conference (EURASIP), 2004.
• [10] Zheng-wei HU and Zhi-yuan XIE, Modification of theoretical fixed-point LMS algorithm for implementation in hardware, 2nd International Symposium on ELECTRICAL COMMERCE AND SECURITY, 2009.
• [11] V. Rodellar, A. Alvarez and E. Marinez, FPGA implementation of an adaptive noise canceller for robust speech enhancement interfaces, 4th Southern Conference on PROGRAMMABLE LOGIC, 2008, San Carlos de Bariloche.
• [12] VR. Mustafa, M. Mohdali, C. Umat and D. Alasadi, Design and implementation of least mean square adaptive filter on altera cyclone II field programmable gate array for active noise control, IEEE Symposium on INDUSTRIAL ELECTRONICS APPLICATIONS (ISIEA), 2009, Kuala Lumpur, Malaysia.
• [13] R. Seifi Majdar and M. Eshghi, Implementation of PBS_LMS algorithm for adaptive filters on FPGA, IEEE TENCON Conference, 2004, Chiang Mai, Thailand.
• [14]`G. Saxena, S. Ganesan and M. Das, Real time implementation of adaptive noise cancellation, IEEE International Conference on ELECTRO/INFORMATION TECHNOLOGY, 2008, No. 4554341, pp. 431-436.