Hardware Design of Image Channel Denoiser for FPGA Embedded Systems

• Autorzy: Sharifi-Tehrani O.

Warianty tytułu

PL

Projekt układu odszumiania w systemie FPGA

• Języki publikacji: EN

Abstrakty

EN

In this article an FPGA-based image channel denoiser using a 1D-standard-LMS algorithm is proposed. The designed core is written in VHDL93 language as basis of 1D-FIR adaptive filter. The proposed core is FPGA-brand-independent, hence can be ported on any brand to create a system-on-chip (SoC). Although using a pure-hardware implementation results in better performance, it is more complex than other structures such as digital signal processors and Hardware/Software co-designs. The results show improvements in area-resource utilization and convergence speed in the designed pure-hardware channel denoiser core.

PL

Zaproponowano metodę usuwania szumów w systemie FPGA bazującą na algorytmie LMS i 1D-SOI filtrze adapatacyjnym. Przedstawiono możliwości zastosowania metody a gotowym układzie zintegrowanym.

Słowa kluczowe

EN

active filters; field programmable gate array (FPGA); image communication; image denoising; system-on-chip

PL

FPGA; filtr adaptacyjny; usuwanie szumu

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2012
• Tom: R. 88, nr 3b
• Strony: 165--167
• Opis fizyczny: Bibliogr. 19 poz., schem., tab., wykr

Twórcy

autor

Sharifi-Tehrani O.

• Young Researchers Club, Majlesi Branch, Islamic Azad University, Majlesi, Iran,

Bibliografia

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