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Hardware Implementations of wavelet transform
Języki publikacji
Abstrakty
Zawarto krótkie wprowadzenie do reprezentacji falkowej sygnałów. Opisano układ filtrów cyfrowych umożliwiający dekompozycję i rekonstrukcję falkową sygnałów. Podano algorytmy i schematy implementacji filtracji cyfrowej w szeregowej arytmetyce rozproszonej. Omówiono sposób dekompozycji tablic LUT oraz realizację decymacji sygnału i implementację filtrów symetrycznych.
Paper contains a short introduction to the wavelet representation of signals and the two-channel filter bank allowing the wavelet decomposition and reconstruction. Efficient distributed arithmetic architectures of digital filtering suitable for FPGA implementation was derived and illustrated. A partitioning algorithm permitting to avoid a large lookup tables was described. Circuit structures implementing signal decimation and making use of filter symmetry was shown.
Wydawca
Rocznik
Tom
Strony
77--81
Opis fizyczny
Bibliogr. 34 poz., rys.
Twórcy
Bibliografia
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- [10] Croisier A., Esteban D. J., Levilion M. E„ Riso V.: Digital Filter for PCM Encoded Signals. U. S. Patent 3777 130, Dec. 4 1973
- [11] Daubechies I.: Orthonormal bases of compactly supported wavelets. Communications in Pure and Applied Mathematics, 41, 1988
- [12] Ding Z.: Image Wavelet Compression Implementation using a Run-Time Reconfigurable Gustom Computing Machine. Master's thesis, Virginia Polytechnic Institute and State University, June 2000
- [13] Xilinx Editor: The Role of Distributed Arithmetic in FPGA-based Signal Processing. Xilinx application note, Xilinx Inc., 1997, http://www.xilinx.com/appnotes/theoryl.pdf
- [14] Grzeszczak A., Mandal M.K., Panchanathan S.: VLSI implementation of discrete wavelet transform. IEEE Transactions on VLSI Systems, 4 (4), December 1996
- [15] Knowles G.: VLSI architecture for discrete wavelet transform. Electron. Lett., 26 (15), July 1990
- [16] Lanq R Plesner E., Schroder H., Spray A.: An efficient systolic architecture for the one-dimensional wavelet transform. In H. H. Szu. editor, Wavelet Applications, Proc. SPIE 2242, 1994, http://citeseer.nj.nec.com/lang94efficient. html
- [17] Lana R Spray A., Schroder H.: 1-d wavelet transform architecture. Technical Report EE9457, Department of Electrical and Computer Engineering, University of Newcastle, Australia, Nov. 17 1994, http//citeseer.nj.nec.com/5495.html
- [18] Lewis A. S., Knowles G.: VLSI architecture for 2-d daubechies wavelet transform without multipliers. Electron. Lett., 27 (2) Jan. 1991
- [19] Łuba T., Zbierzchowski B.: Komputerowe projektowanie układów cyfrowych. Wydawnictwa Komunikacji i Łączności, Warszawa, 2000
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- [21] Łuba T., Zbierzchowski B., Zbysiński P.: Układy reprogramowalne dla potrzeb telekomunikacji cyfrowej. Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne. LXXV (5), 2002
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- [25] Raczinski J. -M., Sladek S., Chevalier L.: Filter Implementation on SYNTHUP. W: Proceedings of the 2nd COST G-6 Workshop on Digital Audio Effects (DAFx99), NTNU, Trondheim, Dec. 9-11 1999
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- [27] Smith M. J. T., Barnwell T. P.: Exact reconstruction techniques for tree-structured subband coders. IEEE Trans, on ASSP, 34, 1986
- [28] Tessier R., Burleson W.: Reconfigurable Computing for Digital Signal Processing: A Survey. Journal of VLSI Signal Processing, 28, 2001, http://www.ecs.umass.edu/ece/tessier/jvsp00.pdf
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- [30] Villasenor J., Mangione-Smith W. H.: Configurable Computing. Scientific American, 276 (6), June 1997, http://www.sciam.com/ /0697issue/0697villasenor.html
- [31] Vishwanath M., Owens R. M., Irwin M. J.: VLSI architectures for discrete wavelet transform. IEEE Trans, on Circuits and Systems, 42 (5),May 1995
- [32] Wasilewski R: 2-D discrete wavelet transform implementation in FPGA device for real-time image processing. W: Wavelet Applications in Signal and Image Processing, San Diego, CA, 30 Jul.-I Aug. 1997
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- [34] White S. A.: Applications of distributed arithmetic to digital signal processing. IEEE ASSP Magazine, 6 (3), July 1989
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