Low-power logic design based on gate driving way considering interconnections capacitances

• Autorzy: Brzozowski I. , Kos A.

Warianty tytułu

PL

Prawdopodobieństwo sterowania bramek jako podstawa projektowania układów cyfrowych o obniżonym poborze mocy z uwzględnieniem pojemności pasożytniczej połączeń

• Języki publikacji: PL

Abstrakty

PL

W artykule przedstawiono metodę projektowania cyfrowych układów scalonych o obniżonym poborze mocy z uwzględnieniem pojemności pasożytniczej połączeń między bramkami. Wykorzystano informacje o zmianie wektorów wejściowych układu oraz wektorów wejściowych bramek – prawdopodobieństwo sterowania bramki. Zaprojektowano układ scalony w technologii CMOS AMS 0.35.m.

EN

This paper presents design method of low-power integrated circuits based on information on primary inputs vectors changes, considering interconnections in real chip. The tested chip was designed in CMOS AMS 0.35�Ým technology. Taking advantage of gate driving way ˇV the reason of a gate switching ˇV two-level logic functions were synthesized. Previously developed design methods for low power synthesis have been modified. Now interconnection capacitance is evaluated and taken into consideration during logic synthesis. Post layout simulations were done for verification.

Słowa kluczowe

PL

układy cyfrowe o obniżonym poborze mocy; połączenia; rozmieszczanie bramek; projektowanie układów scalonych

EN

low-power logic design; interconnections; gate placement; chip design; gate driving way

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2010
• Tom: R. 86, nr 11a
• Strony: 102--106
• Opis fizyczny: Bibliogr. 12 poz., rys., tab.

Twórcy

autor

Brzozowski I.

autor

Kos A.

• AGH University of Science and Technology, Department of Electronics, al. Mickiewicza 30, 30-059 Kraków, Poland,

Bibliografia

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• [2] Roy J.A. , Markov I.L., Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement, IEEE Trans. on CAD, 26 (2007), no. 4, 632-644
• [3] Brzozowski I ., Kos A., A New Approach to Power Estimation and Reduction in CMOS Digital Circuits, Integration, the VLSI Journal, 41 (2008), no. 2, 219-237
• [4] Brzozowski I., Kos A., Modelling of Dynamic Power Dissipation for Static CMOS Gates and Logic Networks, Proc. of the 10th MIXDES Conf., (2003), Poland, 336-341.
• [5] Brzozowski I., Kos A., Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes, LNCS: Integrated Circuit and System Design, Springer Verlag, 3728, (2005), 456-465
• [6] Vaishnav H., Pedram M., PCUBE: A Performance Driven Placement Algorithm for Low Power Design, Proc. of EURODAC '93, (1993), 72-77
• [7] Cheon Y., Ho P-H., Kahng, A.B., Reda, S., Wang Q., Power-Aware Placement, Proc. of 42nd Design Automation Conference, (2005), 759-800
• [8] Brzozowski I., Kos A., Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation, Proc. of the IEEE DDECS Workshop, (2007), Poland, 139-144
• [9] Brzozowski I., Kos A., Calculation Methods of New Circuit Activity Measure for Low Power Modeling, Proc. of Int. Conf. on Signals and Electr. Syst., (2008), Poland, 133-136
• [10] Brzozowski I., Kos A., Power Dissipation Reduction in Two-Level Circuits by Transforming into Three-Level, Proc. of Int. Conf. on Signals and Electr. Syst., (2006), Poland, 617-629
• [11] Ghosh A., Devadas S., Keutzer K., White J., Estimation of Average Switching Activity in Combinational and Sequential Circuits, Proc. of 29th ACM/IEEE Design Automation Conf., (1992), 253-259
• [12] Gimpel J.F., The Minimization of TANT Networks, IEEE Trans. on Electronic Computers, EC-16, (1967), no. 1, 18-38