SI-Studio : environment for SI circuits design automation

• Autorzy: Szczęsny S. , Naumowicz M. , Handkiewicz A.
• Języki publikacji: EN

Abstrakty

EN

The current work is an answer to the problem of designing switched-current (SI) circuits, which is usually a complex issue in the field of microelectronics. The mentioned task is a source of many mistakes and takes a lot of time for designers, therefore authors of the article decided to propose a software solution. This article presents an environment for design automation of analogue circuits in the switched currents technique. It points out the utility advantages of the described tools, which make the work of a VLSI designer much easier, moreover offering a possibility to parameterise the design process considering power consumption, chip area usage and its working speed. It also presents results of an automatic generation of a filter pair circuit, as well as a DCT circuit - automatically generated with the proposed SI-Studio software tools.

Słowa kluczowe

EN

SI circuits; layout; AMPLE; analogue circuits; design automation

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2012
• Tom: Vol. 60, nr 4
• Strony: 757--762
• Opis fizyczny: Bibliogr. 12 poz., rys., tab.

Twórcy

autor

Szczęsny S.

autor

Naumowicz M.

autor

Handkiewicz A.

• Faculty of Computing, Poznań University of Technology, 3A Piotrowo St., 60-965 Poznań, Poland

Bibliografia

• [1] E. Yilmaz and G. Dundar, “Analog layout generator for CMOS circuits”, IEEE Trans. Computer-aided Design of IntegratedCircuits and Systems Archive 28 (1), 32-45 (2009).
• [2] H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F.V. Fernandez, P.-H. Lin, and M. Strasser, “Analog - layout synthesis - recent advances in topological approaches”, Design, Automation& Test in Europe Conf. & Exhibition 1, 274-279 (2009).
• [3] R. Castro-Lopez, O. Guerra, E. Roca, and F.V. Fernandez, “An integrated layout-synthesis approach for analog ICs”, IEEETrans. Computer-aided Design of Integrated Circuits and Systems 27 (7), 1179-1189 (2008).
• [4] A. Handkiewicz, P. Katarzyński, Sz. Szczęsny, J. Wencel, and P. Śniatała, “Analog filter pair design on the basis of a gyratorcapacitor prototype circuit”, Int. J. Circuit Theory and Applications 40 (6), 539-550 (2012).
• [5] A. Handkiewicz, P. Katarzyński, Sz. Szczęsny, “SI filter pair design with the use of a gyrator-capacitor prototype circuit”, IEEJ Int. Analog VLSI Workshop 1, CD-ROM (2010).
• [6] R. Rudnicki, “Choosen tools for automatic design of switchedcurrent circuits”, PhD Dissertation, Poznań University of Technology, Poznań, 2006, (in Polish).
• [7] Handkiewicz, Sz. Szczęsny, M. Naumowicz, M. Melosik, and P. Katarzyński, “Generation of SI filters layout using the row strategy”, Electrical Review 20, 80-83 (2011), (in Polish).
• [8] R. Rudnicki, M. Kropidłowski, and A. Handkiewicz, “Low power switched-current circuits with low sensitivity to the rise/fall time of the clock”, Int. J. Circuit Theory and Applications 38 (5), 471-486 (2010).
• [9] R. Jacob Baker, CMOS, Circuit Design, Layout and Simulation, Wiley-Intercience, IEEE Press, London, 2007.
• [10] A. Handkiewicz, Mixed-Signal Systems: a Guide to CMOS CircuitDesign, John Wiley and Sons, London, 2002.
• [11] A. Handkiewicz, P. Śniatała, G. Pałaszyński, Sz. Szczęsny, P. Katarzyński, M. Melosik, and M. Naumowicz, “Automated DCT layout generation using AMPLE language”, UTP ScientificNotebooks 13, CD-ROM (2010), (in Polish).
• [12] M. P¨ank¨a¨al¨a, K. Virtanen, and A. Paasio, “An analog 2-D DCT processor”, IEEE Trans. Circuits and Systems for Video Technology 16 (10), CD-ROM (2006).