Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits

• Autorzy: Jantos P. , Grzechca D. , Rutkowski J.
• Języki publikacji: EN

Abstrakty

EN

An evolutionary method for analogue integrated circuits diagnosis is presented in this paper. The method allows for global parametric faults localization at the prototype stage of life of an analogue integrated circuit. The presented method is based on the circuit under test response base and the advanced features classification. A classifier is built with the use of evolutionary algorithms, such as differential evolution and gene expression programming. As the proposed diagnosis method might be applied at the production phase there is a method for shortening the diagnosis time suggested. An evolutionary approach has been verified with the use of several exemplary circuits – an oscillator, a band-pass filter and two operational amplifiers. A comparison of the presented algorithm and two classical methods – the linear classifier and the nearest neighborhood method – proves that the heuristic approach allows for acquiring significantly better results.

Słowa kluczowe

EN

analogue integrated circuits; fault diagnosis; localization; identification; evolutionary algorithms

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2012
• Tom: Vol. 60, nr 1
• Strony: 133--142
• Opis fizyczny: Bibliogr. 38 poz., rys., tab.

Twórcy

autor

Jantos P.

autor

Grzechca D.

autor

Rutkowski J.

• Faculty of Automatic Control, Electronics and Computer Sciences, Silesian University of Technology 16 Akademicka St., 44-100 Gliwice, Poland,

Bibliografia

• [1] S. Chakrabarti and A. Chatterjee, “Compact fault dictionary construction for efficient isolation of faults in analog and mixed-signal circuits”, Proc 20th Anniversary Conf. on Advanced Research in VLSI (ARVLSI’99) 1, 327–341 (1999).
• [2] S. Chakrabarti and A. Chatterjee, “Fault diagnosis for mixedsignal electronic systems”, Proc. IEEE Aerospace Conf. 3, 169–179 (1999).
• [3] P. Kabisatpathy, A. Barua, and S. Sinha, Fault Diagnosis of Analogue Integrated Circuits, Springer, London, 2005.
• [4] S. Cherubal and A. Chatterjee, “Test generation based diagnosis of device parameters for analog circuits”, Proc. Conf. on Design Automation and test in Europe 1, 596–602 (2001).
• [5] J.L. Huertas, “Test and design for testability of analog and mixed-signal IC: theoretical basis and pragmatical approaches”, Proc. Eur. Conf. on Circuit Theory and Design 1, 75–156 (1993).
• [6] J.L. Huertas, Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, Boston, 2004.
• [7] M. Lubaszewski, S. Mir, V. Kolarik, C. Nielsen, and B. Courtois, “Design of self-checking fully differential circuits and boards”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 8, 113–27 (2000).
• [8] S. Mir, M. Lubaszewski, and B. Courtois, “Fault-based atpg for linear analog circuits with minimal size multifrequency test sets”, J. Electronic Testing: Theory and Applications 9, 43–57 (1999).
• [9] W. Toczek, “Self-testing of fully differential multistage circuits using common-mode excitation”, Microelectronics Reliability 48, 1890–1899 (2008).
• [10] Z. Czaja, “Using a square-wave signal for fault diagnosis of analog parts of mixed-signal electronic embedded systems”, IEEE Trans. on Instrumentation and Measurement 57 (8), 1589–1595 (2008).
• [11] Z. Czaja, “A diagnosis method of analog parts of mixed-signal systems controlled by microcontrollers”, Measurement 40 (2), 158–170 (2007).
• [12] Z. Czaja and R. Zielonko, “On fault diagnosis of analogue electronic circuits based on transformations in multi-dimensional spaces”, Measurement 35 (3), 293–301 (2004).
• [13] M. Tadeusiewicz, P. Sidyk, and S. Hałgas, “A method for multiple fault diagnosis in analogue circuits”, Proc. Eur. Conf. on Circuit Theory and Design 1, 834–837 (2007).
• [14] T. Golonek and J. Rutkowski, “Genetic-algorithm-based method for optimal analog test points selection”, IEEE Trans. on Circuits and Systems II: Express Briefs 54 (2), 117–121 (2007).
• [15] T. B¨ack, B. Fogel, and Z. Michalewicz, Evolutionary Computation I – Basic Algorithms and Operators, IOP Publishing Ltd, London, 2003.
• [16] T. B¨ack, B. Fogel, and Z. Michalewicz, Evolutionary Computation I – Advanced Algorithms and Operators, IOP Publishing Ltd, London, 2003.
• [17] C. Ferreira, “Gene expression programming: a new adaptive algorithm for solving problems”, Complex Systems 13 (2), 87–129 (2001).
• [18] C. Ferreira, Gene Expression Programming: Mathematical Modeling by an Artificial Intelligence, Springer-Verlag, London, 2006.
• [19] K.V. Price, R.M. Storn, and J.A. Lampinen, Differential Evolution: a Practical Approach to Global Optimization, Springer, London, 2005.
• [20] R. Storn and K.V. Price, “Differential evolution – a simple and efficient adaptive scheme for global optimization over continous spaces”, TR-95-012 Int. Computer Science Institute 1, CD-ROM (1995).
• [21] D. Whitley, “An overview of evolutionary algorithms: practical issues and common pitfalls”, Information and Software Technology 43 (8), 17–831 (2001).
• [22] M. Korzybski, “Dictionary method for multiple soft and catastrophic fault diagnosis based on evolutionary computation”, Proc. Int. Conf. on Signals and Electronic Systems 1, 553–556 (2008).
• [23] P. Jantos, D. Grzechca, T. Golonek, and J. Rutkowski, “Heuristic methods to test frequency optimization for analogue circuits diagnosis”, Bull. Pol. Ac.: Tech. 56 (1), 29–38 (2008).
• [24] P. Jantos, D. Grzechca, and J. Rutkowski, “Global parametric faults identification in analogue electronic circuits”, Metrology and Measurement Systems XVI (3), 391–402 (2009).
• [25] D. Grzechca and J. Rutkowski, “Fault diagnosis in analog electronic circuits – the SVM approach”, Metrology and Measurement Systems XVI (4), 583–598 (2009).
• [26] K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, London, 1994.
• [27] J. Millman, C.C. Halkies, Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill, London, 1972.
• [28] T. Ytterdal, Y. Cheng, and T. Fjeldly, Device Modeling for Analog and RF CMOS Circuit Design, Wiley, London, 2003.
• [29] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, London, 2001.
• [30] P. van Zant, Microchip Fabrication: a Practical Guide to Semiconductor Processing, McGraw-Hill, London, 2004.
• [31] P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, London, 2001.
• [32] P. Jantos, D. Grzechca, T. Golonek, and J. Rutkowski, “The influence of global parametric faults on analogue electronic circuits time domain response features”, Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 1, 299–303 (2008).
• [33] J. Savir and Z. Guo, “The limitations of parametric faults in analog circuits”, IEEE Trans. on Instrumentation and Measurement 52 (5), 1444–1454 (2003).
• [34] M. B¨uhler, J. Koehl and J. Bickford, “Date 2006 special session: DFM/DFY design for manufacturability and yield – influence of process variations in digital, analog and mixed-signal circuit design”, Proc. Design, Automation and Test in Europe 1, 387–392 (2006).
• [35] J. Korbicz, J.M. Kościelny, Z. Kowalczuk, and W, Cholewa, Fault Diagnosis: Models, Artificial Intelligence, Applications, Springer, Berlin, 2004.
• [36] S. Periyalwar, A.E. Marble, S.T. Nugent, and D.N. Swingler, “An adaptive Wiener filter for estimating the time-derivative of the left ventricular pressure signal”, Biomedical Engineering, IEEE Trans. 37, 417–420 (1990).
• [37] Wen Wan-Hui, Qiu Yu-Hui, and Liu Guang-Yuan, “Electrocardiography recording, feature extraction and classification for emotion recognition”, Computer Science and Information Eng., 2009 WRI World Congress 4, 168–172 (2009).
• [38] M. Kyoso, “A technique for avoiding false acceptance in ECG identification”, Biomedical Engineering, IEEE EMBS Asian-Pacific Conf. 1, 190–191 (2003).