Pipeline processing in low-density parity-check codes hardware decoder

• Autorzy: Sułek W.
• Języki publikacji: EN

Abstrakty

EN

Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

Słowa kluczowe

EN

channel coding; LDPC codes; iterative decoding; decoder implementation; pipelined processing

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2011
• Tom: Vol. 59, nr 2
• Strony: 149--155
• Opis fizyczny: Bibliogr. 15 poz., rys., tab.

Twórcy

autor

Sułek W.

• Institute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, Poland,

Bibliografia

• [1] R.G. Gallager, Low-Density Parity-Check Codes, MIT Press, Cambridge, 1963.
• [2] D.J.C. MacKay, “Good error-correcting codes based on very sparse matrices”, IEEE Trans. Inf. Theory 45 (2), 399–431 (1999).
• [3] M.M. Mansour and N.R. Shanbhag, “High throughput LDPC decoders”, IEEE Trans. VLSI Syst. 11 (6), 976–996 (2003).
• [4] H. Zhong and T. Zhang, “Block-LDPC: A practical LDPC coding system design approach”, IEEE Trans. Circuits Syst. 1, 52 (4), 766–775 (2005).
• [5] W. Sułek, “Seed graph expansion for construction of structured LDPC codes”, IEEE Int. Symposium on Wireless Communication Systems (ISWCS) 1, 216–220 (2009).
• [6] S. Lin and D.J. Costello, Jr., Error Control Coding: Fundamentals and Applications, 2nd Edition, Prentice-Hall Inc., New Jersey, 2004.
• [7] J. Chen, A. Dholakia, E. Eleftheriou, M.P.C. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes”, IEEE Trans. on Communications 53 (8), 1288–1299 (2005).
• [8] M.M. Mansour, “A turbo-decoding message-passing algorithm for sparse parity-check matrix codes”, IEEE Trans. Signal Process. 54 (11), 4376–4392 (2006).
• [9] M.M. Mansour and N.R. Shanbhag, “A 640-Mb/s 2048-Bit programmable LDPC decoder chip”, IEEE J. Solid-State Circuits 41 (3), 684–698 (2006).
• [10] L. Yang, H. Liu, and C.J.R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder”, IEEE Trans. Circuits Syst. 1, 53 (4), 892–903 (2006).
• [11] M. Rovini, N.E. L’Insalata, F. Rossi, and L. Fanucci, “VLSI design of a high-throughput multi-rate decoder for structured LDPC codes”, DSD 2005 Euromicro Conf. Digital System Design 1, 202–209 (2005).
• [12] X.-Y. Hu, E. Eleftheriou, D.M. Arnold, and A. Dholakia, “Efficient implementations of the sum-product algorithm for decoding LDPC codes”, IEEE Globecom 1, 1036–1036E (2001).
• [13] W. Sułek and D. Kania, “Code construction algorithm for architecture aware LDPC codes with low-error-floor”, Proc. IEEE Region 8 Int. Conf. on Computational Technologies in Electrical and Electronics Engineering – SIBIRCON 2008 1, 1–6 (2008).
• [14] X.-Y. Hu, E. Eleftheriou, and D.M. Arnold, “Regular and irregular progressive edge-growth tanner graphs”, IEEE Trans. Inf. Theory 51 (1), 386–398 (2005).
• [15] J. Chen and M.P.C. Fossorier, “Near optimum universal belief propagation based decoding of low-density parity check codes”, IEEE Trans. on Communications 50 (3), 406–414 (2002).