Nowe metody sprzętowo-programowego przetwarzania sygnałów i obrazów dla potrzeb systemów informacyjnych

• Autorzy: Łuba T. , Rawski M.

Warianty tytułu

EN

Novel Digital Signal and Image Processing Software and Hardware for Information Systems

• Języki publikacji: PL

Abstrakty

PL

Dokonano przeglądu osiągnięć związanych z projektem badawczym realizowanym we współpracy z Singapurem. Przedstawiono wyniki prac w zakresie podstaw teoretycznych konstrukcji algorytmów syntezy logicznej oraz implementacji tych algorytmów w strukturach programowalnych. Omówiono sprzętowe systemy DSP realizowane w najnowszych strukturach CPLD/FPGA i optymalizowane narzędziami komputerowego wspomagania projektowania dostosowanymi do specyficznych cech struktur programowalnych.

EN

Main outcomes of the Joint Singapore-Poland Project are presented. Theoretical results underlying the development of logic synthesis algorithms and examples of implementation of such algorithms with programmable devices are discussed. New DSP processing systems based on hardware designed with use of the most recent CPLD/FPGA structures and software designed to efficiently utilize specific features of these programmable structures are presented.

Słowa kluczowe

PL

układy cyfrowe; układy DSP; projektowanie; struktury programowalne FPGA/CPLD

EN

digital circuits; DSP systems; design; FPGA/CPLD programmable devices

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne
• Rocznik: 2010
• Tom: nr 4
• Strony: 105--110
• Opis fizyczny: Bibliogr. 35 poz., rys., tab.

Twórcy

autor

Łuba T.

autor

Rawski M.

• Instytut Telekomunikacji, Politechnika Warszawska,

Bibliografia

• [1] Falkowski B.J., Lozano C.C., Luba I: Family of Fastest Linearly Independent Transforms over GF(3): Generation, Relations and Hardware Implementation. Multiple-Valued Logic and Soft Computing Journal, USA, vol. 13, no. 4-6, September 2007 (Artykuł na stronie czasopisma: http://www.oldcitypublishing .com/MVLSC/MVLSC% 2013.4-6%20abstracts/379.html)
• [2] Rawski M., Falkowski B.J., Luba T.: Digital Signal Processing Designing forFPGAArchitectures. Facia Universitatis (Nisz), Series: Electronics and Energetics, vol. 20, no. 3, Nisz, December 2007
• [3] Rawski M., Tomaszewicz R, Falkowski B.J., Luba T: Application of Advanced Logic Synthesis in FPGA-based Implementations of Digital Fitters. DASIP'2007 - Design & Architectures for Signal and Image Processing, Grenoble, France, 27-20 November, 2007 (Materiały na PenDrive stron 8)
• [4] Falkowski B. J., Lozano C., Luba T.: Properties and Relations of New Fastest Linearly Independent Arithmetic Transforms for Ternary Functions. Proceedings of the 15th European Signal Processing Conference, EUSIPCO 2007, Poznań, Poland, 3-4 September, 2007 (drukiem wydane abstrakty, stron 6)
• [5] Tomaszewicz R, Nowicka M., Falkowski B.J., Luba T: Logic Synthesis Importance in FPGA-based Designing of Image Signal Processing Systems. Proceedings of the 14th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS MIXDES 2007, Ciechocinek, Poland 21-23 June, 2007
• [6] Rawski M., Wojtyński M., Wojciechowski T, Majkowski R: Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures. Proceedings of the 14th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS MIXDES 2007, Ciechocinek, Poland 21-23 June, 2007
• [7] Rawski M., Falkowski B.J., Luba I: Decomposition-Based Synthesis in Implementation of Digital Filters for Wavelet Transform Application Targeted FPGA Dewces. IEEE Instrumentation and Measurement Technology Conference Proceedings IMTC/2007 (materiaty na CD, stron 6), Warszawa, Poland, May 1-3, 2007
• [8] Borowik G., Falkowski B. J., Luba T: Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's. l E Workshop on Design and Diagnostics of Electronic Circuits and Systems, Kraków, Poland, April 11-13, 2007
• [9] Morawiecki R, Rawski M., Selvaraj H.: Input Variable Partitioning Method of Functional Decomposition of Functions Specified by Large Truth Tab/es. International Conference Computational Intelligence and Multimedia Applications 2007, vol. II, Sivakasi, India, December 13-15, 2007
• [10] Luba T(red.), Rawski M., Tomaszewicz R, Zbierzchowski B.: Programowalne układy przetwarzania sygnałów i informacji. Wydawnictwa Komunikacji i Łączności, Warszawa 2008
• [11] Falkowski B.J., Lozano C.C.,Luba T: Arithmetic and Boolean techniques forderivation of system reliabilityexpressions. Electronics and Telecommunications Quarterly, vol. 54, no 2, 07/2008
• [12] Borowik G.: lmproved State Encoding for FSM Implementation in FPGA Structures with Embedded Memory Blocks. Electronics and Telecommunications duarterly, vol. 54, no 1, 03/2008
• [13] Rawski M., Selvaraj H., Falkowski B.J., Luba T: Chapter XII: Significance of Logic Synthesis in FPGA-Based Design of Image and Signal Processing Systems. Pattern Recognition Technologies and Applications: Recent Advances, April 2008
• [14] Morawiecki R, Rawski M., Selvaraj H.: Application of Functional Decomposition in Synthesis of Boolean Function Sets. Proceedings International Conference on Systems Engineering ICSEng 2008 (Editet by Henry Selvaraj and Mariusz Rawski), Las Vegas, Nevada, USA, 19-21 August 2008
• [15] Rawski M., Falkowski B.J., Luba T: Logic Synthesis Method for FPGAs with Embedded Memory Blocks. ISCAS 2008, 2008 IEEE International Symposium on Circuits and Systems, publication on CD, Seattle, Washington, USA, May 18-21, 2008
• [16] Majchrzyk M., Borowik G., Darakchiev R.: Realizacja dekodera adresów z zastosowaniem w pełni określonych funkcji boolowskich. XI Konferencja Naukowa Reprogramowalne Układy Cyfrowe RUC'2008, materiaty CD, Szczecin, 15-16 maja 2008
• [17] Luba T, Borowik G., Kraśniewski A.: Synthesis of finite state machines for implementation with programmable Structures. Electronics and Telecommunications Ouarterly, vol. 55, no 2, 02/2009
• [18] Rawski M., Borowik G., Luba T, Tomaszewicz P, Falkowski B.J.: Logic Synthesis Strategy for FPGAs with Embedded Memory Blocks. Proceedings of the 16th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS MIXDES 2009, Lodź, Poland 25-27 June, 2009
• [19] Borowik G., Luba T: Decomposing Pattern Matching Circuit, 12th International Workshop on Computer Aided Systems Theory - EUROCAST 2009, Extender abstracts, Las Palmas de Grań Canaria, Feb. 2009
• [20] Falkowski B.J., Sahoo S.K., Luba T: Two Novel Methods for Compression of Fluorescent Dye Celi Images. Proceedings of the 16th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS MIXDES 2009, Łódź, Poland 25-27 June, 2009
• [21] Lozano C.C., Falkowski B.J., Luba T: New Classes Quaternary Linearly Independent Arithmetic Transforms. Proceedings of the 16th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS MIXDES 2009, Łódź, Poland 25-27 June, 2009
• [22] Labiak G., Borowik G.: State chart Diagrams Implementation in FPGA Structures with Embedded Memory Blocks. DESDes'09, Preprints of the 4th IFAC Workshop Discrete-Event System Design 2009, Gandia Beach, Spain 6-8 October 2009
• [23] Borowik G., Luba T., Tomaszewicz P.: A notion of r-admissibility and its application in logic Synthesis. DESDes'09, Preprints of the 4th IFAC Workshop Discrete-Event System Design 2009, Gandia Beach, Spain 6-8 October 2009
• [24] Tomaszewicz R, Staworko M., Rawski M., Luba T: Implementacja sprzętowa dwuwymiarowej transformacji falkowej w układach FPGA, Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne, nr 12/2009
• [25] Morawiecki R: Functional Decomposition System Dedicated to Mutti-Output Boolean Functions, Electronics and Telecommunications Quarterly, vol. 55, no 3, 2009
• [26] Lozano C.C., Falkowski B.J., Luba T.: Two Classes of Fixed Polarity Linearly Independent Arithmetic Transforms for Quatemary Functions, European Signal Processing Conference, August 2009
• [27] Borowik G., Luba T: Decomposing Pattern Matching Circuit, In Computer Aided Systems Theory - EUROCAST 2009, ISSN 0302 - 9743, vol. 5717, Springer 2009
• [28] Rawski M., Borowik G., Luba T., Tomaszewicz R, Falkowski B.J.: Logic Synthesis Strategy for FPGAs with Embedded Memory Blocks. Electrical Review Journal, submitted Sep-09
• [29] Morawiecki R: Dekompozycja funkcjonalna zespołów funkcji boolowskich, Rozprawa doktorska, Instytut Telekomunikacji PW, listopad 2009
• [30] Furtak M., Wolos B.: Implementacja sprzętowa dwuwymiarowej transformacji falkowej, praca magisterska, opiekun naukowy doc. Dr inż. Bogdan Zbierzchowski, Politechnika Warszawska, 2009
• [31] Nowicka M., Majchrzyk M.: Opis oprogramowania: Program Demain, Generator LUT, opracowanie wewnętrzne, Instytut Telekomunikacji PW, wrzesień 2008
• [32] Dipert B.: Counting on Gate Counts? Don't count on it, EDN Magazine, August 3, 1998
• [33] Ishihara N., Abe K.: An Efficient 2-D DWT Architecture with Reduced Memory Accesses for Low Energy Consumption, From Proceeding Circuits, Signals, and Systems (CSS 2006), November 2006
• [34] Meyer-Baese U.: Digital Signal Processing with Field Programmable Gate Arrays, Second Edition, Springer Verlag, Berlin, 2004
• [35] Sasao T, Iguchi Y, Suzuki T: On LUT Cascade realizations of FIR Filters, DSD 2005, Proc. Eighth Euromicro Conference on DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools, IEEE Computer Society, Christophe Wolinski (Editor), Porto, Portugal, 2005