Power equalization of AES FPGA implementation

• Autorzy: Strachacki M. , Szczepański S.
• Języki publikacji: EN

Abstrakty

EN

This paper briefly introduces side channel attacks on cryptographic hardware with special emphasis on differential power analysis (DPA). Based on existing countermeasures against DPA, design method combining power equalization for synchronous and combinatorial circuits has been proposed. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) device using the standard and power-equalized methods. Power traces for DPA have been collected using XPower tool. Simulation results show that standard AES implementation can be broken after N=500 encryptions, while power-equalized counterpart shows no correlation between power consumption and the cipher key after N=2000 encryptions.

Słowa kluczowe

EN

AES; FPGA; cryptography; side channel attack; DPA; power analysis; power equalization

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2010
• Tom: Vol. 58, nr 1
• Strony: 125--128
• Opis fizyczny: Bibliogr. 14 poz., rys.

Twórcy

autor

Strachacki M.

autor

Szczepański S.

• Department of Microelectronic Systems, Gdansk University of Technology, 11/12 Narutowicza St., 80-952 Gdansk, Poland,

Bibliografia

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