Heat dissipation and temperature distribution in long interconnect lines

• Autorzy: Gnidzińska K. , Mey G. , Napieralski A.
• Języki publikacji: EN

Abstrakty

EN

Thermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it is compulsory to give priority to the time delay aspect and then the optimized solution is found by making the power dissipation as homogenous as possible and consequently the temperature distribution T (relative to ambient) as low as possible. The technology used for simulations is 65 nm node. The occurring phenomena have been described in a quantitative and qualitative way.

Słowa kluczowe

EN

interconnect lines; heat dissipation; delay; temperature distribution

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2010
• Tom: Vol. 58, nr 1
• Strony: 119--124
• Opis fizyczny: Bibliogr. 8 poz., rys., tab.

Twórcy

autor

Gnidzińska K.

autor

Mey G.

autor

Napieralski A.

• Department of Microelectronics and Computer Science, Technical University of Lodz, 221/223 Wolczanska St., 90-924 Lodz, Poland,

Bibliografia

• [1] International Technology Roadmap for Semiconductors, http://www.itrs.net/, 2005.
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• [3] Y.I. Ismail, E.G. Friedman, and J.L. Neves, “Dynamic and short-circuit power of CMOS gates driving lossless transmission lines”, IEEE Trans. Circuits and Systems I: Analog and Digital Signal Processing 46 (8), 950–961 (1999).
• [4] Predictive Technology Model (PTM), http://ptm.asu.edu/, 2007.
• [5] B. Vermeersch and G. De Mey, “Thermal impedance plots of micro-scaled devices”, Microelectronics and Reliability 46 (1), 174–177 (2006).
• [6] G. De Mey, Various Applications of the Boundary Element Method, Editura Universitatii din Oradea, Oradea, 2002.
• [7] Y.A. C¸ engel, Heat Transfer: a Practical Approach, McGraw-Hill, London, 2002.
• [8] T.-Y. Chiang, K. Banerjee, and K.C. Saraswat, “Analytical thermal model for multilevel VLSI interconnects incorporating via effect”, IEEE Electron Device Letters 23 (1), 31–33 (2002).