On reducing PLC response time

• Autorzy: Chmiel M.
• Języki publikacji: EN

Abstrakty

EN

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don't disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-so Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.

Słowa kluczowe

EN

programmable logic controller; bit-byte structure of CPU; control program; scan time; response time; throughput time; Timer Function; counter function; concurrent operation

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2008
• Tom: Vol. 56, nr 3
• Strony: 229--238
• Opis fizyczny: Bibliogr. 13 poz., rys., tab.

Twórcy

autor

Chmiel M.

• Institute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, Poland,

Bibliografia

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• [3] H. Berger, Automating with STEP 7 in LAD and FED SIMATIC S7-300/400 Programmable Controllers, Siemens AG, Monachium, 2001.
• [4] M. Chmiel and E. Hrynkiewicz, "Remarks on parallel bit-byte CPU structures of programmable logic controllers", Int. Workshop on Discrete Event System Design, DESDes 1, 147-152 (2001).
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• [6] Siemens A.G., Simatic S7-200 Programmable Controller - System Manual, Siemens AG, Monachium, 2002.
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• [8] J. Donandt, "Improving response time of programmable logic controllers by use of a Boolean coprocessor", IEEE Comput. Soc. Press. 4, 167-169 (1989).
• [9] M. Chmiel and E. Hrynkiewicz, "Remarks on parallel bit-byte CPU structures of programmable logic controllers", in: Design of Embedded Control Systems, ed. M. A. Adamski, A. Karatkevich, and M. Wygrzyn, pp. 231-242, Springer Science + Business Media, Inc., Berlin, 2005.
• [10] M. Chmiel and E. Hrynkiewicz, "Concurrent operation of the processors in bit-byte CPU of industrial PLC", Int. Workshop on Programmable Devices and Systems, PDS'04 1, 15-20 (2004).
• [11] M. Chmiel, E. Hrynkiewicz, and A. Milik, "Concurrent operation of the processors in bit-byte CPU of a PLC", Preprints of the IFAC World Congress D, 44-49 (2005).
• [12] M. Chmiel and E. Hrynkiewicz, "Improving of concurrent operation of the bit-byte PLC CPU", Int. Conf. on Programmable Devices and Systems, PDS'06 1, 132-137, (2006).
• [13] M. Chmiel, A. Malcher, and A. Nowara, "A control system for a metal sheet pickling line", Machine Technologies and Materials, 20-21 (1997), (in Polish).