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Tytuł artykułu

Optimization of compositional microprogram control units implemented on system-on-chip

Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In the article two methods of designing of CMCU are proposed. Both methods are oriented on application in the system-on-a-chip where dedicated memories can be used for implementation of control memory of CMCU. First method is based on the CMCU with base structure that was previously used only to the programmable devices (PLD). In the article some required changes in the structure of CMCU in order to use System-On-Chip devices (SoC) with built-in memories were proposed. Second method is based on using of part of the address of microinstruction as a code of the output o operational linear chain (OLC). The results of research of effectiveness of both methods are shown. The researches conducted by authors base shown that the best under the characteristics of interpreted flow-chart method of CMCU permits to decrease an amount of logic-elements in comparison with CMCU with base structure up to 35+42%.
Rocznik
Strony
7--22
Opis fizyczny
Bibliogr. 15 poz., rys., tab.
Twórcy
autor
  • Instytut Informatyki i Elektroniki, Uniwersytet Zielonogórski ul. Podgórna 50, 65-246 Zielona Góra
Bibliografia
  • [1] Baranov S., Logic Synthesis for Control Automata. Kluwer Academic Publishers, 1994.
  • [2] Barkalov A.A., Principles of optimization of logical circuit of Moore finite-state machine, Cybernetics and System Analysis 1998, 1.
  • [3] Barkalov A.A., Synthesis of Control Units on PLDs, DonNTU, Donetsk 2002 (in Russian).
  • [4] Barkalov A.A., Synthesis of Operational Units, DonNTU, Donetsk 2003 (in Russian).
  • [5] Barkalov A., Wiśniewski R., Design of control units with transformation of the number of transaction, Proceedings 11th International Conference "Mixed Design of Integrated Circuits and System", 24-26 June 2004, Szczecin, Poland.
  • [6] Barkalov A., Wiśniewski R., Optimization of compositional microprogram control unit with elementary operational linear chains, Control Systems and Computers 2004.
  • [7] Brown S., Vernesic Z., Fundamentals of Digital Logic with VHDL Design, McGraw Hill, 2000.
  • [8] De Micheli G., Synthesis and Optimization of Digital Circuits, McGraw Hill, New York 1994.
  • [9] Grushnitsky R., Mursaev A., Ugrjumov E., Development of systems on chips with programmable logic, SPb: BHV, Petersburg 2002 (in Russian).
  • [10] Iwai H., Future CMOS Scaling, Proceedings 11th International Conference "Mixed Design of Integrated Circuits and System", Szczecin, Poland, 2004.
  • [11] Jenkins J., Design with FPGAs and CPLDs, Prentice Hall, 1995, 273.
  • [12] Synteza układów cyfrowych, Praca zbiorowa pod red. T. Łuby, WKŁ, Warszawa 2003.
  • [13] Salcic Z., VHDL and FPGAs in digital systems design, prototyping and customization, Kluwer Academic Publishers, 1998.
  • [14] Sasao T., Switching theory for logic synthesis, Kluwer Academic Publishers, 1999.
  • [15] Solovjev V., Design of digital systems using the programmable logic integrate circuits, Moscow, Hot line - Telecom, 2001 (in Russian).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPG5-0019-0001
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