BDD-based decompositions of multiple output logic functions

• Autorzy: Dzikowski A. , Hrynkiewicz E.
• Języki publikacji: EN

Abstrakty

EN

The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solu-tions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main ad-vantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved.

Słowa kluczowe

EN

binary decision diagrams; decomposition; FPGA

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2006
• Tom: Vol. 54, nr 4
• Strony: 489--498
• Opis fizyczny: Bibliogr. 14 poz., rys., tab.

Twórcy

autor

Dzikowski A.

autor

Hrynkiewicz E.

• Institute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, Poland,

Bibliografia

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