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The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solu-tions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main ad-vantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved.
Słowa kluczowe
Rocznik
Tom
Strony
489--498
Opis fizyczny
Bibliogr. 14 poz., rys., tab.
Twórcy
autor
autor
- Institute of Electronics, Silesian University of Technology, 16 Akademicka St., 44-100 Gliwice, Poland, andrzej.dzikowski@polsl.pl
Bibliografia
- [1] R.E. Bryant, “Graph-based algorithms for Boolean function manipulation”, IEEE Trans. Computers C-35, 667–691 (1986).
- [2] S.B. Akers, “Binary decision diagrams”, IEEE Transactions on Computers C-27 (6), 509–516 (1978).
- [3] R.L. Ashenhurst, “The decomposition of switching function”, Proc. Int. Symposium on the Theory of Switching, 1957.
- [4] R. Murgai, R.K. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis for Field-Programmable Gate Arrays, Kluwer Academic Publishers, Boston–Dordrecht–London, 1995.
- [5] A. Dzikowski and E. Hrynkiewicz, “Methods of decomposition of multiple output logic functions with using ROBDD diagrams”, IV National Scientific Conference, Programmable Logic Devices, 19–28 (2001).
- [6] A. Dzikowski and E. Hrynkiewicz, “Advanced area decomposition of multiple output logic functions with using ROBDD diagrams”, II National Electronics Conference II, 393–398 (2003).
- [7] A. Dzikowski and E. Hrynkiewicz, “Modification of area decomposition of multiple output logic functions with using of ROBDD diagrams”, III National Electronics Conference I, 285–290 (2004).
- [8] A. Dzikowski and E. Hrynkiewicz, “Modification of area decomposition of multiple output logic functions in shorting propagation time”, IV National Electronics Conference I, 171–17 (2005).
- [9] A benchmark set, University of California, Los Angeles, VLSI CAD Laboratory, http://vlsicad.cs.ucla.edu/ cheese/benchmarks.html
- [10] R. Lasocki, “Decomposition of functional interrelationships determined on finite sets”, PhD Thesis, Warsaw University of Technology, Warsaw, 1998, (in Polish).
- [11] M. Nowicka, T. Łuba, and H. Selvaraj, “Multilevel decomposition strategies in decomposition-based algorithms and tools”, Int. Workshop on Logic and Architecture Synthesis, 129–136 (1997).
- [12] J-D. Huang, J-Y. Jou, and W-Z Shen, “An iterative area/performance trade off algorithm for LUT-based FPGA technology mapping”, IEEE Trans. on Very Large Integration (VLSI) Systems 8(4), 392–400 (2000).
- [13] D. Kania, “The heuristic method for decomposition of Boolean functions and dedicated for matrix-type FPGA circuits with application of the techniques of advanced decomposition”, Quarterly of Electronics and Telecommunication 2 (46), 191–206 (2000).
- [14] D. Kania: “Multiple decomposition in logic synthesis for FPGA devices”, Electronics 2–3, 43–46 (2002).
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Bibliografia
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bwmeta1.element.baztech-article-BPG5-0016-0035