Transresistance CMOS neuron for adaptive neural networks implemented in hardware

• Autorzy: Wojtyna R. , Talaśka T.
• Języki publikacji: EN

Abstrakty

EN

A simple analog circuit is presented which can play a neuron role in static-model-based neural networks implemented in the form of au integrated circuit. Operating in a transresistance mode it is suited to cooperate with transconductance synapses. As a result, its input signal is a current which is a sum of currents coming from the synapses. Summation of the currents is realized in a made at the neuron input. The circuit bas two outputs and provides a step function signal at one output and a linear function one at the other. Activation threshold of the step output can be conveniently controlled by means of a voltage. Having two outputs, the neuron is attractive to be used in networks taking advantage of fuzzy logic. It is built of only five MOS transistors, can operate with very law supply voltages, consumes a very law power when processing the input signals, and no power in the absence of input signals. Simulation as well as experimental results are shown to be in a good agreement with theoretical predictions. The presented results concern a 0.35 [mi]m CMOS process and a prototype fabricated in the framework of Europractice.

Słowa kluczowe

EN

neural networks; learning on silicon; hardware intelligence; CMOS analog circuits; low-power electronics

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2006
• Tom: Vol. 54, nr 4
• Strony: 443--448
• Opis fizyczny: Bibliogr. 17 poz., rys., tab.

Twórcy

autor

Wojtyna R.

autor

Talaśka T.

• Institute of Telecommunication, University of Technology and Agńculture, 7 Kaliskiego St., 85-796 Bydgoszcz, Poland,

Bibliografia

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• [7] P. Grad, “Switched-feddback analog memories for CMOS neuroprocessing”, Ph.D. Dissertation, University of Technology and Agriculture, Bydgoszcz, 2003, (in Polish).
• [8] R. Wojtyna and T. Talaśka, “Improved power-saving synapse for hardware implemented ANN’s”, Int. Conf. on Signals and Electronic Systems ICSES, 27–30 (2004).
• [9] R. Wojtyna and T. Talaśka “Simple low-power CMOS neuron to be used with transconductance synapses”, IEEE Workshop Signal Signal Processing, 21–26 (2004).
• [10] R.Wojtyna and T. Talaśka, “CMOS neuron with step and linear activation functions”, State Electronics Conference KKE, 79–84 (2005).
• [11] T. Talaśka, R. Wojtyna, and R. Długosz, “Hardware implemented neural network model with unsupervised learning on silicon”, Int. Workshop MIXDES’2005, 133–136 (2005).
• [12] R. Wojtyna, “Simple CMOS transconductance-mode differential squarer”, IEEE Workshop Signal Processing’2005, Poznań, 171–177 (2005).
• [13] R. Wojtyna, “Current-mode analog square rooter for hardware neuroprocessing”, IEEE Workshop Signal Processing’2006, Poznań, 61–64 (2006).
• [14] T. Tala´ska, R. Wojtyna, R. Długosz, and K. Iniewski, “Implementation of the conscience mechanism for Kohonen’s Neural Network in CMOS 0.18 ¹m technology”, International Conference Mixed Design of Integrated Circuits and Systems MIXDES’2006, Gdynia, 319–315 (2006).
• [15] T. Tala´ska, R. Wojtyna, R. Długosz, K. Iniewski, and W. Pedrycz, “Analog-counter-based conscience mechanism in Kohonen’s neural network implemented in CMOS 0.18 ¹m technology”, IEEE Workshop on Signal Processing Systems, Banff, Canada, 420–425 (2006).
• [16] R. Długosz, T. Talaśka, and R. Wojtyna, “New binary-treebased winner-takes-all circuit for learning on silicon Kohonen’s networks”, International Conference on Signals and Electronic Systems, ICSES 2006, Łódź , 441–444 (2006).
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