Evolutionary design and optimization of combinational digital circuits with respect to transistor count

• Autorzy: Słowik A. , Białko M.
• Języki publikacji: EN

Abstrakty

EN

In the paper an application of evolutionary algorithm to design and optimization of combinational digital circuits with respect to transistor count is presented. Multiple layer chromosomes increasing the algorithm efficiency are introduced. Four combinational circuits with truth tables chosen from literature are designed using proposed method. Obtained results are in many cases better than those obtained using other methods.

Słowa kluczowe

EN

artificial intelligence; evolutionary algorithm; combinational digital circuits; design; optimizion

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2006
• Tom: Vol. 54, nr 4
• Strony: 437--442
• Opis fizyczny: Bibliogr. 10 poz., rys.

Twórcy

autor

Słowik A.

autor

Białko M.

• Department of Electronics and Computer Science, Technical University of Koszalin, 2 Śniadeckich St., 75-453 Koszalin, Poland,

Bibliografia

• [1] M. Karnaugh, “A map method for synthesis of combinational logic circuits”, AIEE Trans. Communications and Electronic 72 (I), 593–599 (1953).
• [2] W.V. Quine, “A way to simplify truth function”, American Mathematical Monthly 62 (9), 627–631 (1955).
• [3] E.J. McCluskey, “Minimization of Boolean function”, Bell Systems Technical Journal 35 (5), 1417–1444 (1956).
• [4] J. Greene, “Simulated evolution and adaptive search in engineering design”, in 2nd Online Workshop on Soft Computing, 1997.
• [5] C. A. Coello, A. D. Christiansen, and A. H. Aguirre, “Use of evolutionary techniques to automate the design of combinational circuits”, Int. J. Smart Engineering System Design 2 (4), 299–314 (2001).
• [6] C. A. Coello, A. D. Christiansen, and A. H. Aguirre, “Automated design of combinational logic circuits using genetic algorithms”, Proc. Int. Conf. on Artificial Neural Nets and Genetic Algorithms, 335–338 (1997).
• [7] C. A. Coello, A. H. Aguirre, and B. P. Buckles, “Evolutionary multiobjective design of combinational logic circuits”, Proc. 2nd NASA/DoD Workshop on Evolvable Hardware, 161–170 (2000).
• [8] A. Słowik and M. Białko, “Design and optimization of combinational digital circuits using modified evolutionary algorithm”, Proc. 7th Int. Conf. on Artifficial Intelligence and Soft Computing 3070, 468–473 (2004).
• [9] A. Słowik and M. Białko, “Modified version of roulette selection for evolution algorithm – the fan selection”, Proc. 7th Int. Conf. on Artifficial Intelligence and Soft Computing ICAISC 3070, 474–479 (2004).
• [10] P. Nilagupta and N. Ou-thong, “Logic function minimization base on transistor count using genetic algorithm”, Proc. 3rd Information and Computer Engineering Postgraduate Workshop, Songkla, Thailand, 2003.