Effects of interconnection inductances on VLSI circuit performance

• Autorzy: Piwowarska E.
• Języki publikacji: EN

Abstrakty

EN

The inductance of on-chip interconnections is usually neglected in simulation of CMOS circuits behaviour. This assumption becomes not valid for modern technologies with higher frequency and greater parasitic RLC parameters of interconnections. This paper describes briefly the model of interconnection and presents the method for R, L parameter calculating in the range of frequency suitable for VLSI CMOS circuits. The calculated values are used for simulating the inductive effects in IC's. The significance of the on-chip interconnection inductance is discussed.

Słowa kluczowe

EN

VLSI circuits; interconnection parasitics; crosstalk; switching noise

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 1998
• Tom: Vol. 46, nr 3
• Strony: 353--361
• Opis fizyczny: Bibliogr. 8 poz., 6 rys.

Twórcy

autor

Piwowarska E.

• Institute of Microelectronics and Optoelectronics, University of Technology, ul. Koszykowa 75, 00-662 Warszawa, Poland.