Logic Synthesis Method for Power Dissipation Reduction in Combinational Digital Circuits

• Autorzy: Brzozowski I. , Kos A.
• Języki publikacji: EN

Abstrakty

EN

In the paper the authors summerise their works on power dissipation reducing in combinational digital VLSI circuits. The reduction is obtained thanks to proper logic synthesis which consists in the decrease of circuit switching activity and is a part of complex multiobjective optimisation. As a consequence, less complicated, smaller, more reliable and faster digital circuits can be designed. The proposed new synthesis method is illustrated with some examples. The benchmark is included.

Słowa kluczowe

EN

low power design; VLSI digital circuits; power consumption minimisation; switching activity reduction; logic synthesis; multiobjective optimisation; benchmark

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2001
• Tom: vol. 49, nr 4
• Strony: 581--594
• Opis fizyczny: 12 rys., 3 tabele, bibliogr. 11 poz

Twórcy

autor

Brzozowski I.

autor

Kos A.

• University of Mining and Metallurgy, Department of Electronics, 30-059 Kraków, ul. Mickiewicza 30 (Akademia Górniczo-Hutnicza, Katedra Elektroniki),