Comparison of Various SC FIR Filter Structures on the Basis of their CMOS Realization and Simulation in the PSPICE Program

• Autorzy: Dąbrowski A. , Długosz R.
• Języki publikacji: EN

Abstrakty

EN

In this paper switched-capacitor finite impulse response (SC FIR) filter structures are considered and developed. Their performance (i.e., general features, quality of operation, influence of parasitic capacitance, the chip area requirements, etc.) are analyzed and compared for various possible SC FIR structures. The comparisons are not only based on the method for the chip area estimation, proposed by authors in [1], but also on the precise chip area determination by means of the simulation of the considered circuits using the PSPICE program and by means of their design in the [formula] CMOS technology. Special attention is paid in this paper to the decomposition of FIR delay-line filter structures into second order sections (and possibly into a single first order section). The importance of such decomposition for the reduction of the required chip area occurred to be evident during the design process.

Słowa kluczowe

EN

switched-capacitor (SC) circuits; SC FIR filters; CMOS integrated circuits; SPICE simulation

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2001
• Tom: vol. 49, nr 1
• Strony: 59--79
• Opis fizyczny: 19 rys., 4 tabele, bibliogr. 9 poz

Twórcy

autor

Dąbrowski A.

autor

Długosz R.

• Institute of Electronics and Telecommunications, Poznań University of Technology, Piotrowo 3A, PL-60-965 Ponań, Poland (Instytut Elektroniki i Telekomunikacji Politechniki Poznańskiej)