Comparison of Various SC FIR Filter Structures on the Basis of their CMOS Realization and Simulation in the PSPICE Program

• Autorzy: Dąbrowski A. , Długosz R.
• Języki publikacji: EN

Abstrakty

EN

In this paper switched-capacitor finite impulse response (SC FIR) filter structures are considered and developed. Their performance (i.e., general features, quality of operation, influence of parasitic capacitance, the chip area requirements, etc.) are analyzed and compared for various possible SC FIR structures. The comparisons are not only based on the method for the chip area estimation, proposed by authors in [1], but also on the precise chip area determination by means of the simulation of the considered circuits using the PSPICE program and by means of their design in the [formula] CMOS technology. Special attention is paid in this paper to the decomposition of FIR delay-line filter structures into second order sections (and possibly into a single first order section). The importance of such decomposition for the reduction of the required chip area occurred to be evident during the design process.

Słowa kluczowe

EN

switched-capacitor (SC) circuits; SC FIR filters; CMOS integrated circuits; SPICE simulation

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2001
• Tom: vol. 49, nr 1
• Strony: 59--79
• Opis fizyczny: 19 rys., 4 tabele, bibliogr. 9 poz

Twórcy

autor

Dąbrowski A.

autor

Długosz R.

• Institute of Electronics and Telecommunications, Poznań University of Technology, Piotrowo 3A, PL-60-965 Ponań, Poland (Instytut Elektroniki i Telekomunikacji Politechniki Poznańskiej)

Bibliografia

• [1] A. Dąbrowski, R. Długosz, Chip area estimation for SC FIR filter structures in CMOS technology, Chapter 22 in Mixed design of integrated circuits and systems, Kluwer, Boston 1998.
• [2] A. Dąbrowski, Multirate and multiphase switched-capacitors circuits, Chapman & Hall, London 1996.
• [3] A. Dąbrowski, U. Menzi, G. S. Moschytz, Design of switched-capacitor FIR filters with applications to a low-power MFSK receiver, IEE Proceedings – G, 139, 4, (August 1992).
• [4] G. S. Moschytz, The morphological approach to network and circuits design, IEEE Trans. Circuits Syst., CAS-23, 4, (1976) 239-242.
• [5] R. Gregorian, G. C. Temes, Analog MOS integrated circuits for signal processing, John Wiley & Sons, New York 1985.
• [6] R. Długosz, A. Dąbrowski, CMOS realization and comparison of basic SC FIR filter structures, Proceedings of the 5th International Conference of Mixed Design of Integrated Circuits and Systems 1998.
• [7] R. Długosz, A. Dąbrowski, Comparison of SC FIR filter structures by simulations in the PSPICE program, Proceedings of the XXIst KKTOiUE, Poznań-Kiekrz, 1998.
• [8] A. Dąbrowski, U. Menzi, G. S. Moschytz, Offset-compensated switched-capacitoT delay circuit that is insensitive to stray capacitance and to capacitor mismatch, Electron. Lett., 25, 6, (1989) 387-389.
• [9] C. Fischer, Analog PIR filters by switched-capacitor techniques, IEEE Trans. Circuits and Syst., CAS-37, 6, (1990) 808-814.