An Accurate DC MOSFET Model for VLSI Simulation

• Autorzy: Ati A.A. , Napieralski A. , Napieralska M. , Ciota Z.
• Języki publikacji: EN

Abstrakty

EN

A new accurate, physical, continuous, and simple DC MOSFET model for short-channel devices down to submicron channel lengths is presented in this paper for the simulation of VLSI circuits. The proposed model is based on the Charge-Sheet Approximation (CSA) and describes efficiently the I-V characteristics from subthreshold to strong inversion region as well as from the linear to the saturation region of operation with a single current equation. The model takes into account the major physical effects in state-of-the-art of deep-submicron MOSFET devices such as short and narrow channel effects on threshold voltage, carrier velocity saturation, BIBL, CLM, and mobility reduction due to vertical field. The effect of parasitic source/drain series resistance to the drain current characteristics is explicitly included in the model. The model is physically based, so the continuity of drain current, output conductance, and transconductance is ensured over all [formula], and [formula] bias conditions. Therefore, the model is very suitable for VLSI simulation. The model accuracy is verified by comparison with experimental data for MOSFET with different channel lengths and widths.

Słowa kluczowe

EN

charge-sheet model; submicron MOSFETs; VLSI simulation; analog circuits

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2000
• Tom: Vol. 48, nr 1
• Strony: 61--71
• Opis fizyczny: 4 rys., bibliogr. 13 poz.

Twórcy

autor

Ati A.A.

autor

Napieralski A.

autor

Napieralska M.

autor

Ciota Z.

• Technical University of Łódź, Department of Microelectronics and Computers Science, Al. Politechniki 11, 93-590 Łódź, Poland (Katedra Mikroelektroniki i Technik Informatycznych Politechniki Łódzkiej),