Compact Modelling of Ultra Deep Submicron CMOS Devices

• Autorzy: Grabiński W. , Sallese J.M. , Bucher M. , Krummenacher F.
• Języki publikacji: EN

Abstrakty

EN

The technology of CMOS very large-scale integrated circuits (VLSI) has achieved remarkable advances over last 25 years and the progress is expected to continue well into this century. However, even before the minimum feature sizes of the active VLSI devices reach the fundamental limits, this evolution is expected to encounter severe technological and economic problems when the dimensions go below sub-quarter micron, the so called ultra deep submicron (UDSM). There are many physical effects that need to be addressed while modelling UDSM devices , such as quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects. In this paper, the advances in compact MOSFET devices will be illustrated using application examples of the EPEL-EKV model.

Słowa kluczowe

EN

ultra deep submicron (UDSM) technology; EPEL-EKV compact MOS-FET model; low power and RF applications

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2002
• Tom: Vol. 50, Nr 1
• Strony: 13--27
• Opis fizyczny: Bibliogr. 28 poz., 6 rys., tab.

Twórcy

autor

Grabiński W.

• Motorola, Geneva, Modelling Center

autor

Sallese J.M.

• Electronics Laboratory, EPFL, Lausanne, Switzerland

autor

Bucher M.

• NTUA, Athens, Greece

autor

Krummenacher F.

• Electronics Laboratory, EPFL, Lausanne, Switzerland

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