Design of a 3.3V Four-Quadrant Analog CMOS Multiplier

• Autorzy: Szczepański S. , Kozieł S.
• Języki publikacji: EN

Abstrakty

EN

The two CMOS four-quadrant analog multipliers that can operate from a supply voltage of 3.3V are presented. The proposed circuit technique has been developed using MOS transistors working both in saturation and nonsaturation regions. Simulation results have shown that the introduced circuit based on MOS devices operating in the linear region has the total harmonic distortion (THD) less than 0.75% for input signal up to 2Vpp with 10MHz sine wave. A 3-dB bandwidth about 1GHz is attainable from either input. A power consumption of the circuit is 1.4mW.

Słowa kluczowe

EN

analog multipliers; CMOS integrated circuit; transconductance element

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2003
• Tom: Vol. 51, nr 2
• Strony: 163--172
• Opis fizyczny: 5 rys., bibliogr. 17 poz.

Twórcy

autor

Szczepański S.

• Gdańk University of Technology, Faculty of Electronics, Telecommunications and Informatics, Narutowicza 11/12, 80-952 Gdańsk, Poland (Wydział Elektroniki, Telekomunikacji i Informatyki, Politechnika Gdańska)

autor

Kozieł S.

• Gdańk University of Technology, Faculty of Electronics, Telecommunications and Informatics, Narutowicza 11/12, 80-952 Gdańsk, Poland (Wydział Elektroniki, Telekomunikacji i Informatyki, Politechnika Gdańska)

Bibliografia

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