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Problemy minimalizacji mocy pobieranej przez układy logiki programowalnej

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Warianty tytułu
EN
Problems of minimization of power consumed by programmable logic devices
Języki publikacji
PL
Abstrakty
PL
Przedstawiona praca prezentuje problematykę energii w schematach logiki programowalnej. Pokazane są najpopularniejsze aspekty nowoczesnych metod minimalizacji mocy pobieranej przez schematy sekwencyjne. Analiza różnych metod pokazuje w najszerszej perspektywie możliwości badań dotyczących zarządzania energią pobieraną, konsumowaną i traconą.
EN
The problems of the consumed in the sequential logic power also deferent methods of their solving are addressed. Also the low-power techniques, used in different levels of the technology are considered. The aim of the work is to systematize the most popular, known methods and to show the ways of development it at the branch of the programmable logic.
Rocznik
Tom
Z.1
Strony
21--29
Opis fizyczny
Bibliogr. 26 poz., wykr.
Twórcy
  • Politechnika Białostocka, Katedra Systemów Komputerowych, ul. Wiejska 45 A, 15-351 Białystok
autor
  • Politechnika Białostocka, Katedra Systemów Komputerowych, ul. Wiejska 45 A, 15-351 Białystok
Bibliografia
  • [1] Xunwei Wu, Pedram M. Low power sequential circuit design using priority encoding and clock gating. Proceedings of ISLPED'00: ACM. 2000, pp.143-8
  • [2] Wu X, Pedram M, Wang L. Multi-code state assignment for low power design. JP, ]EE Proc: CDS, vol.147, no.5, Oct. 2000, pp.271-5.
  • [3] Bacchetta P, Daldoss L, Sciuto D, Silvano C. Low-power state assignment techniques for finite state machines. IEEE ISCS. Proc. vol.2, 2000, pp.641-4
  • [4] Marculescu D, Marculescu R, Pedram M. Theoretical bounds for switching activity analysis in finite-state machines.IEEE Trans. on VLSI Sys. June 2000, pp.335-9
  • [5] Ahmad I, Dhodhi MK. State assignment of finite-state machines. JP, IEE Proc.-E CDT Jan.2000, pp.15-22
  • [6] Zhi-Hong W. En-Cheng L. Jianbang L. Ting-Chi W. Power minimization in LUT-based FPGA technology mapping. Proc of the ASP-DAC IEEE 2001, pp.635-40. Piscataway, NJ, USA.
  • [7] Wolff FG. Knieser MJ. Weyer DJ. Papachristou CA. High-level low power FPGA design methodology. Proc of the IEEE 2000 NAECON 2000 pp.554- 9. Piscataway, NJ, USA.
  • [8] Garcia A. Burleson W. Danger JL. Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. 2000 IEEE ISET pp.561-4
  • [9] Yonghee [m. Kaushik Roy. A novel high-performance predictable circuit architecture for the deep sub-micron era. Proc of the IEEE 2000 Custom Integrated Circuits Conference.
  • [10] Takeuchi K. Satoh S$. [mamiya K. Sakui K. A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J of SSC May 2000, pp.672-81.
  • [11] Ranjan RK, Singhal V, Somenzi F, Brayton RK. On the optimization power of retiming and resynthesis transformations. CP, 1998 IEEE/ACM IC on CAD. Digest of Technical Papers., pp.402-7. New York, NY, USA.
  • [12] Marculescu D, Marculescu R, Pedram M. Theoretical bounds for switching activity analysis in finite-state machines.CP, Proc. 1998 ISLPED, pp.36-41
  • [13] Koegst M, Franke G, Rulke S, Feske K. Multi-criterial state assignment for low power FSM design. PC, Proc.24th EUROMICRO Conference IEEE CS, 1998, pp.261-8 vol.1,USA
  • [14] Kashirova L, Tveretina O. Entropy-based design of low power FSMs. CP, Proc.24thEUROMICRO Conf IEEE, 1998, pp.188-91 vol.1
  • [15] Takahashi H. Mizushima S. A 1.2 V, 30 MIPS, 0.3 mA/MIPSŚ and 200 MIPS, 0.58 mA/MIPS digital signal processors. IEICE Tran on Electronics, vol.E83- C, no.2, Feb. 2000, pp.1 79-85. Japan.
  • [16] Jan-Min H. Feng-Yi C. TingTing H. A re-engineering approach to low power FPGA design using SPFD. Proc 1998 35th DAC. IEEE. 1998, pp.722-5. New York, NY, USA.
  • [17] Tisserand A. Marchal P. Piguet C., An on-line arithmetic based FPGA for lowpower custom computing., Field Programmable Logic and Applications. 9th International Workshop,FPL'99. pp.264-73. Germany.
  • [18] Chattopadhyay S$, Chaudhuri PP. Genetic algorithm based approach for integrated state assignment and flip flop selection in finite state machine synthesis. CP Proc 1 1th IC on VLSI Design, EEE CS 1997, pp.522-7.
  • [19] Bloch M. Lauterbach C. Weber W. High efficiency charge pump circuit for negative high voltage generation at ŻV supply voltage. ESSCIRC '98. Proc of the 24th ESSCIRC
  • [20] Katkoori S. Vemuri R. Simulation based architectural power estimation for PLA-based controllers. 1996 [S$ on L PED. IEEE. 1996, pp.121-4. New York, NY, USA
  • [21] Surti P, Chao L-F. Controller power estimation using information from behavioral description. [Conference Paper] 1996 IEEE, ISCAS. Part vol.4, 1996, pp.679-82
  • [22] Tuagi A. Entropic bounds on FSM switching. IEEE Trans. on VLSISys, vol.5, no.4, Dec. 1997, pp.456-64.
  • [23] Hartenstein R. Herz M. Hoffmann T. Nageldinger U., Using the KressArray for reconfigurable computing. SPIE-Int. SOE Proc of SI SOE, vol.3526, 1998, pp.150-61.
  • [24] Ming-Der Shieh, Wann-Shyang Ju, Ming-Hwa Sheu. Low-power state assignment for asynchronous finite state machines. CP, Proc of the 39th MS on CS IEEE vol.3, 1996, pp.1325-8 vol
  • [25] Koegst M, Franke G, Feske K. State assignment for FSM low power design. [Conference Paper] Proc EURO-DAC '96. EURO-VHDL '96 Soc. Press. 1996, pp.28-33.
  • [26] Eisenring M. Teich J. Interfacing hardware and software. Field-Programmable Logic and Applications. From FPGAs to Computing Paradigm. 8th IW, FPL'98, pp.520-4, Germany.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BPB2-0005-0087
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