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A Hybrid CPU/GPU Cluster for Encryption and Decryption of Large Amounts of Data

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The main advantage of a distributed computing system over standalone computer is an ability to share the workload between cores, processors and computers. In our paper we present a hybrid cluster system - a novel computing architecture with multi-core CPUs working together with many-core GPUs. It integrates two types of CPU, i.e., Intel and AMD processor with advanced graphics processing units, adequately, Nvidia Tesla and AMD FirePro (formerly ATI). Our CPU/GPU cluster is dedicated to perform massive parallel computations which is a common approach in cryptanalysis and cryptography. The efficiency of parallel implementations of selected data encryption and decryption algorithms are presented to illustrate the performance of our system.
Rocznik
Tom
Strony
32--39
Opis fizyczny
Bibliogr. 22 poz., rys., tab.
Twórcy
autor
autor
  • Institute of Control and Computation Engineering, Warsaw University of Technology, Nowowiejska st 15/19, 00-665 Warsaw, Poland, ens@ia.pw.edu.pl
Bibliografia
  • [1] F. Berman, G. Fox, and A. J. G. Hey, Grid Computing: Making the Global Infrastructure a Reality. New York: Wiley, 2003.
  • [2] A. Karbowski and E. Niewiadomska-Szynkiewicz, Parallel and distributed computing (in Polish). WUT Publishing House, 2009.
  • [3] Wen-Mei W. Hwu (Ed.), GPU Computing Gems Emerald Edition. Morgan Kaufman, 2011.
  • [4] R. Lottiaux, B. Boissinot, P. Gallard, G. Vallee, and C. Morin, “Openmosix, openssi and kerrighed: a comparative study”, in Proc. IEEE Int. Symp. Cluster Comput. and the Grid CCGrid’05, Cardiff, UK, 2005, vol. 2, pp. 1016–1023.
  • [5] A. Barak and A. Shiloh, “The mosix virtual opencl (VCL) cluster platform”, in Proc. Intel Eur. Res. Innov. Conf., Leixlip, Ireland, 2011, p. 196.
  • [6] V. Kindratenko, J. Enos, G. Shi, M. Showerman, G. Arnold, J. Stone, J. Phillips, and W. Hwu, “GPU clusters for high-performance computing”, in Proc. Worksh. Paral. Programm. Accelerator Clust. PPAC’09, New Orleans, LA, USA, 2009.
  • [7] A. Di Biagio, A. Barenghi, G. Agosta, and G. Pelosi, “Design of a parallel AES for graphics hardware using the CUDA framework”, in Proc. 23rd IEEE Int. Parallel Distrib. Proces. Symp. IPDPS 2009, Rome, Italy, 2009, pp. 1–8.
  • [8] J. W. Bos, D. A. Osvik, and D. Stefan, “Fast implementations of AES on various platforms”, Tech. rep., Cryptology ePrint Archive, Report 2009/501, 2009 [Online]. Available: http://eprint.iacr.org
  • [9] D. Le, J. Chang, X. Gou, A. Zhang, and C. Lu, “Parallel aes algorithm for fast data encryption on GPU”, in Proc. 2nd Int. Conf. Comp. Engin. Technol. ICCET 2010, Chengdu, China, 2010, vol. 6, pp. V6–1.
  • [10] C. Mei, H. Jiang, and J. Jenness, “CUDA-based aes parallelization with fine-tuned GPU memory utilization”, in Proc. IEEE Int. Symp. Parallel & Distrib. Proces., Worksh. and Phd Forum IPDPSW 2010, Atlanta, Georgia, USA, 2010, pp. 1–7.
  • [11] C. Li, H. Wu, S. Chen, X. Li, and D. Guo, “Efficient implementation for MD5-RC4 encryption using GPU with CUDA”, in Proc. 3rd Int. Conf. Anti-Counterfeiting, Secur., Identif. Commun. ASID 2009, Hong Kong, China, 2009, pp. 167–170.
  • [12] Z. Wang, J. Graham, N. Ajam, and H. Jiang, “Design and optimization of hybrid MD5-blowfish encryption on GPUs”, in Proc. Int. Conf. Paral. Distrib. Proces. Techn. Appl. PDPTA’11, Las Vegas, Nevada, USA, 2011, pp. 18–21.
  • [13] G. Liu, H. An, W. Han, G. Xu, P. Yao, M. Xu, X. Hao, and Y. Wang, “A program behavior study of block cryptography algorithms on GPGPU”, in Proc. 4th Int. Conf. Frontier Comp. Sci. Technol. FCST’09, Shanghai, China, 2009, pp. 33–39.
  • [14] S. Fleissner, “GPU-accelerated montgomery exponentiation”, in Proc. Int. Conf. Computat. Sci. ICCS 2007, Beijing, China, 2007, pp. 213–220, 2007.
  • [15] O. Harrison and J. Waldron, “Efficient acceleration of asymmetric cryptography on graphics hardware”, in Proc. 2nd Int. Conf. Cryptol. in Africa AFRICACRYPT 2009, Gammarth, Tunisia, 2009, pp. 350–367.
  • [16] A. Moss, D. Page, and N. P. Smart, “Toward acceleration of RSA using 3D graphics hardware”, in Proc. 11th IMA Int. Conf. Crypography and Coding, Springer, 2007, pp. 364–383.
  • [17] J. Hermans, F. Vercauteren, and B. Preneel, “Speed records for NTRU”, in Proc. Topics in Cryptol. CT-RSA 2010, San Francisco, CA, USA, 2010, pp. 73–88.
  • [18] J. Hermans, F. Vercauteren, and B. Preneel, “Implementing NTRU on a GPU”, Darmstadt University of Technology, Darmstadt, Ger- many, 2009.
  • [19] M. Marks, “Enhancing wsn localization robustness utilizing HPC environment”, in Proc. Eur. Conf. Model. Simul. ECMS 2012, Koblenz, Germany, 2012, pp. 167–170.
  • [20] W. Szynkiewicz and J. Błaszczyk, “Optimization-based approach to path planning for closed chain robot systems”, Int. J. Appl. Mathema. Comp. Sci. ACMS, vol. 21, no. 4, pp. 659–670, 2011.
  • [21] M. Marks, J. Jantura, E. Niewiadomska-Szynkiewicz, P. Strzelczyk, and K. Gózdz, “Heterogenous GPU/GPU cluster for high performance computing in cryptography”, Comp. Sci., vol. 14, no. 2, pp. 63–79, 2012.
  • [22] A. J. Menezes, P. C. van Oorschot, and S. A. Vanstone, Handbook of Applied Cryptography. New York: CRC Press, 1996.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BATA-0017-0004
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