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The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma

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Języki publikacji
EN
Abstrakty
EN
This study describes the effects of high temperature annealing performed on structures fluorinated during initial silicon dioxide reactive ion etching (RIE) process in CF4 plasma prior to the plasma enhanced chemical vapour deposition (PECVD) of the final oxide. The obtained results show that fluorine incorporated at the PECVD oxide/Si interface during RIE is very stable even at high temperatures. Application of fluorination and high temperature annealing during oxide layer fabrication significantly improved the properties of the interface (Ditmb decreased), as well as those of the bulk of the oxide layer (Qeff decreased). The integrity of the oxide (higher Vbd ) and its uniformity (Vbd distribution) are also improved.
Rocznik
Tom
Strony
25--28
Opis fizyczny
Bibliogr. 9 poz., rys., tab.
Twórcy
autor
autor
autor
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa st 75, 00-662 Warsaw, Poland; Motor Transport Institute, Jagiellońska st 80, 03-301 Warsaw, Poland, mkalisz1@mion.elka.pw.edu.pl
Bibliografia
  • [1] Y. Kuo-Lang, J. Ming-Jer, and H. Jenn-Gwo, “Fluorinated thin gate oxides prepared by room temperature deposition followed by furnace oxidation”, Solid-State Electron., vol. 43, no. 3, pp. 671–676, 1999.
  • [2] L. Vishnubhotla, T. P. Ma, H.-H. Tseng, and P. J. Tobin, “Interface trap generation and electron trapping in fluorinated SiO2”, Appl. Phys. Lett., vol. 59, no. 27, pp. 3595–3597, 1991.
  • [3] P. J. Wright and K. C. Saraswat, “The effect of fluorine in silicon dioxide gate dielectrics”, IEEE Trans. Electron. Dev., vol. 36, no. 5, pp. 879–889, 1989.
  • [4] J. G. Huang and R. J. Jaccodine, “Fast growth of thin gate dielectrics by thermal oxidation of Si in N2O gas ambient with low concentration of NF3 addition”, J. Electrochem Soc., vol. 140, no. 2, p. L15, 1993.
  • [5] Y. Nishioka, K. Ohyu, Y. Ohij, N. Natuaki, K. Mukai, and T.-P. Ma, “Hot-electron hardened Si-gate MOSFET utilizing F implantation”, IEEE Electron Dev. Lett., vol. 10, no. 4, pp. 141–143, 1989.
  • [6] P. J. Wright, N. Kasai, S. Inoue, and K. C. Sarawat, “Hot-electron immunity of SiO2 dielectrics with fluorine incorporation”, IEEE Electron Dev. Lett., vol. 10, no. 8, pp. 347–348, 1989.
  • [7] S. P. Jeng, T. P. Ma, R. Canteri, M. Anderle, and G. W. Rubloff, “Anomalous diffusion of fluorine in silicon”, Appl. Phys. Lett., vol. 61, no. 11, pp. 1310–1312, 1992.
  • [8] M. Kalisz, G. Głuszko, and R. B. Beck, “Novel method of improving electrical properties of thin PECVD oxide films by fluorination of silicon surface region by RIE in RF CF4 plasma”, J. Telecommun. Inform. Technol., no. 1, pp. 20–24, 2010.
  • [9] M. Kalisz, R. B. Beck, and M. Ćwil, “Reactive-ion-etching (RIE) process in CF4 plasma as a method of fluorine implantation”, Vacuum, vol. 82, no. 10, pp. 1046–1050, 2008.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BATA-0008-0023
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