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Novel Method of Improving Electrical Properties of Thin PECVD Oxide Films by Fluorination of Silicon Surface Region by RIE in RF CF4 Plasma

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Języki publikacji
EN
Abstrakty
EN
This study describes a novel technique to form good quality low temperature oxide (< 350 C degree). Low temperature oxide was formed by N2O + SiH4:N2 plasma in a plasma enhanced chemical vapour deposition (PECVD) system on the silicon surface reactively etched in CF4 plasma (RIE - reactive ion etching). The fabricated oxide demonstrated excellent (for low temperature dielectric formation process) currentvoltage (I-V) characteristics, such as: low leakage current, high breakdown voltage and good reliability. Experimental results indicate that the proposed method of fluorine incorporation into the SiO2/Si inteface improves electrical parameters of MOS structures.
Rocznik
Tom
Strony
20--24
Opis fizyczny
Bibliogr. 10 poz., rys., tab.
Twórcy
autor
autor
autor
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa st 75, 00-662 Warsaw, Poland; Motor Transport Institute, Jagiellońska st 80, 03-301 Warsaw, Poland, mkalisz1@mion.elka.pw.edu.pl
Bibliografia
  • [1] Y. Mitani, H. Satake, Y. Nakasaki, and A. Toriumi, “Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides”, IEEE Trans. Electron Dev., vol. 50, no. 11, pp. 2221–2226, 2003.
  • [2] Y. Nishioka, K. Ohyu, Y. Ohji, N. Natuaki, K. Mukai, and T. P. Ma, “Hot-electron hardened Si-gate MOSFET utilizing F implantation”, IEEE Electron Device Lett., vol. 10, no. 4, pp. 141–143, 1989.
  • [3] P. Wrigh, N. Kasai, S. Inoue, and K. C. Saraswat, “Hot electron immunity of SiO2 dielectrics with fluorine incorporation”, IEEE Electron Dev. Lett., vol. 10, no. 8, pp. 347–348, 1989.
  • [4] X. W. Wang, A. Balasinski, T. P. Ma, and Y. Nishioka, “Pre-oxidation fluorine implantation in Si process-related MOS characteristics”, J. Electrochem. Soc., vol. 139, no. 1, pp. 238–241, 1992.
  • [5] H. H. Tseng, P. J. Topin, F. K. Baker, J. R. Pfiester, K. Evans, and P. L. Fejes, “The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in P+ gate chanel MOSFET’s with fluorine incorporation”, IEEE Trans. Electron Dev., vol. 39, no. 7, pp. 1687–1693, 1992.
  • [6] E. F. da Silva Jr., Y. Nishioka, and T. P. Ma, “Radiation response of MOS capacitors containing fluorinated oxide”, IEEE Trans. Electron Dev., vol. 34, no. 6, pp. 1190–1195, 1987.
  • [7] J. Ahn, G. Q. Lo, W. Ting, D. L. Kwong, J. Kuehne, and C. W. Magee, “Radiation hardered metal-oxide-semiconductor devices with gate dielectrics grown by rapid thermal processing in O2 with diluted NF3”, Appl. Phys. Lett., vol. 58, no. 4, pp. 425–427, 1991.
  • [8] J-W. Lee, Y. Li, and S. M. Sze, “Highly reliable low temperature ultrathin oxides grown using N2O plasma”, WSEAS Trans. Electron., vol. 1, no. 1, pp. 72–76, 2004.
  • [9] M. Kalisz, R. B. Beck, and M. Ćwil, “Reactive ion etching process (RIE) in CF4 plasma as a method of fluorine implantation”, Vaccum, vol. 82, no. 10, pp. 1046–1050, 2008.
  • [10] S. K. Lai and D. R. Young, “Effects of avalanche injection of electrons into silicon-dioxide – generation of fast and slow interface states”, J. Appl. Phys., vol. 52, no. 10, pp. 6231–6240, 1981.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BATA-0008-0022
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