Analysis of the Dispersion of Electrical Parameters and Characteristics of FinFET Devices

• Autorzy: Malinowski A. , Tomaszewski D. , Łukasiak L. , Jakubowski A. , Sekine M. , Hori M. , Korwin-Pawlowski M. L.
• Języki publikacji: EN

Abstrakty

EN

Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure, composition and powering on the FinFET topography. Next, the most important geometric parameters of the FinFETs have been varied and the electrical characteristics have been calculated in order to evaluate the sensitivity of the FinFET electrical parameters on possible FinFET structure variability.

Słowa kluczowe

EN

FinFET; line edge roughness; parameter variability; plasma etching; technology computer aided design (TCAD)

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2009
• Tom: nr 4
• Strony: 45--50
• Opis fizyczny: Bibliogr. 4 poz., rys., tab.

Twórcy

autor

Malinowski A.

autor

Tomaszewski D.

autor

Łukasiak L.

autor

Jakubowski A.

autor

Sekine M.

autor

Hori M.

autor

Korwin-Pawlowski M. L.

• Department of Electrical Engineering and Computer Science School of Engineering, Nagoya University, IB building 3F 331, Furo-cho, Chikusa-ku, Nagoya City, Aichi, 464-8603, Japan,

Bibliografia

• [1] J. P. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Springer, 2008.
• [2] H. Kawasaki et al., “FinFET process and integration technology for high performance LSI in 22 nm node and beyond”, in Proc. Junct. Technol. 2007 Int. Worksh., Kyoto, Japan, 2007, pp. 3–8.
• [3] A. Yagishita, “FinFET SRAM process technology for hp 32 nm node and beyond”, in Proc. Integr. Circ. Des. Technol. ICICDT’07. IEEE Int. Conf., Austin, USA, 2007, pp. 1–4.
• [4] Y. K. Choi et al., “Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era”, Solid-State Electron., vol. 46, pp. 1595–1601, 2002.