Prospects and Development of Vertical Normally-off JFETs in SiC

• Autorzy: Bakowski M.
• Języki publikacji: EN

Abstrakty

EN

This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25 C degree to 250 C degree. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

Słowa kluczowe

EN

JFET cascode; normally-off; SiC; vertical JFET

• Wydawca: Instytut Łączności - Państwowy Instytut Badawczy
• Czasopismo: Journal of Telecommunications and Information Technology
• Rocznik: 2009
• Tom: nr 4
• Strony: 25--36
• Opis fizyczny: Bibliogr. 19 poz., rys., tab.

Twórcy

autor

Bakowski M.

• Acreo AB, Electrum 236, SE-164 40 Kista, Sweden,

Bibliografia

• [1] P. Friedrichs, H. Mitlehner, K. O. Dohnke, D. Peters, R. Schörner, U. Weinert, E. Baudelot, and D. Stephani, “SiC power devices with low on-resistance for fast switching applications”, in Proc. 12th Int. Symp. Pow. Semicond. Dev. ICs, Toulouse, France, 2000, p. 213.
• [2] Y. Tanaka, M. Okamotu, A. Takatsuka, K. Arai, T. Yatsuo, K. Yano, and M. Kasuga,“700 V 1.0 mW · cm2 buried gate SiC-SIT (SiCBGSIT)”, IEEE Electron Dev. Lett., vol. 27, no. 11, pp. 908–910, 2006.
• [3] R. K. Malhan, Y. Takeuchi, M. Kataoka, A.-P. Mihaila, S. J. Rashid, F. Udrea, and G. A. J. Amaratunga, “Normally-off trench JFET technology in 4H silicon carbide”, Microelectron. Eng., vol. 83, iss. 1, pp. 107–110, 2006.
• [4] S. Krishnaswami, A. Agarwal, S. H. Ryu, C. Capell, J. Richmond, J. Palmour, S. Balachandran, T. P. Chow, S. Bayne, B. Gail, K. Jones, and C. Scozzie, “1000 V, 30 A 4H-SiC BJTs with high current gain”, IEEE Electron Dev. Lett., vol 26, no. 3, pp. 175–177, 2005.
• [5] M. Bakowski, “Status and prospects of SiC power devices”, IEEE Trans. Ind. Appl., vol. 126, no. 4, pp. 391–399, 2006.
• [6] R. K. Malhan, H. Nakamura, S. Onda, D. Nakamura, and K. Hara, “Impact of SiC structural defects on the degradation phenomenon of bipolar SiC devices”, Mater. Sci. Forum, vol. 433–436, pp. 917–920, 2003.
• [7] B. °Allebrand and H.-P. Nee, “On the possibility to use SiC JFETs in power electronic circuits”, in Proc. 9th Conf. Pow. Electron. Appl., EPE’2001, Graz, Austria, 2001.
• [8] M. Bakowski and U. Gustafsson, “Unipolar and bipolar SiC integral cascoded switches with MOS and junction gate – simulation study”, Mater. Sci. Forum, vol. 389–393, pp. 1321–1324, 2002.
• [9] M. L. Heldwein and J. W. Kolar, “A silicon carbide JFET gate driver circuit allowing short commutation times for sparse matrix converter applications”, in Proc. Nineteenth Ann. IEEE Appl. Pow. Electron. Conf. Expos., Anaheim, USA, 2004, vol. 1, pp. 116–121.
• [10] P. Friedrichs, H. Mitlehner, K. W. Bartsch, O. Dohnke, R. Kattschmidt, U. Weinert, B. Weis, and D. Stephani, “Static and dynamic characteristic of 4H-SiC JFETs designed for different blocking categories”, Mater. Sci. Forum, vol. 338–342, pp. 1243–1246, 2000.
• [11] M. Bakowski, “Analysis of unipolar and bipolar SiC cascaded switches with MOS gate”, Mater. Sci. Forum, vol. 433–436, pp. 801–804, 2003.
• [12] V. Veliadis, T.McNutt, M. Snook, H. Hearne, P. Potyraj, J. Junghans, and C. Scozzie, “Large area silicon carbide vertical JFETs for 1200 V cascode switch operation”, Int. J. Pow. Manag. Electron., vol. 2008, art. id. 523721, 8 p., 2008.
• [13] D. Stephani and P. Friedrichs, “Silicon carbide junction field effect transistors”, Int. J. High Speed Electron. Syst., vol. 16, no. 3, pp. 825–854, 2006.
• [14] M. Bakowski, U. Gustafsson, and U. Lindefelt, “Simulation of SiC high power devices”, Phys. Stat. Sol. A, vol. 162, pp. 421–440, 1997.
• [15] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
• [16] J. K. Lim and M. Bakowski, “Analysis of 1.2 kV SiC buried grid VJFETs” (to be published in Phys. Scripta T, 2009).
• [17] Y. Tanaka, K. Yano, M. Okamoto, A. Takatsuka, K. Arai, and T. Yatsuo, “1270 V, 1.21 mWcm2 SiC buried gate static induction transistors (SiC-BGSITs)”, Mater. Sci. Forum, vol. 600–603, pp. 1071–1074, 2009.
• [18] R. K. Malhan, M. Bakowski, Y. Takeuchi, N. Sugiyama, and A. Schöner, “Design, process, and performance of all-epitaxial normally-off SiC JFETs”, Phys. Stat. Sol. A, vol. 206, iss. 10, pp. 2308–2328, 2009.
• [19] R. K. Malhan, S. J. Rashid, M. Kataoka, Y. Takeuchi, N. Sugiyama, F. Udrea, G. A. J. Amaratunga, and T. Reimann, “Switching performance of epitraxially grown normally-off 4H-SiC JFET”, Mater. Sci. Forum, vol. 600–603, pp. 1067–1070, 2009.